Conference Paper

Communication Architectures for Dynamically Reconfigurable FPGA Designs.

DOI: 10.1109/IPDPS.2007.370364 Conference: 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), Proceedings, 26-30 March 2007, Long Beach, California, USA
Source: DBLP


This paper gives a survey of communication architectures which allow for dynamically exchangeable hardware modules. Four different architectures are compared in terms of reconfiguration capabilities, performance, flexibility and hardware requirements. A set of parameters for the classification of the different communication architectures is presented and the pro and cons of each architecture are elaborated. The analysis takes a minimal communication system for connecting four hardware modules as a common basis for the comparison of the diverse data given in the papers on the different architectures.

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    ABSTRACT: In this paper we present a solution where only one FPGA is needed in a host coupled system, in which the FPGA can be reconfigured by a user application during run-time without loosing the host link connection. A hardware infrastructure on the FPGA and the software framework ACCFS (ACCelerator File System) on the host system is provided to the user which allow easy handling of reconfiguration and communication between the host and the FPGA. Such a system can be used for offloading compute kernels on the FPGA in high performance computing or exchanging functionality in highly available systems during run-time without loosing the host link during reconfiguration. The implementation was done for a HyperTransport coupled FPGA. The design of a HyperTransport cave was extended in such a way that it provides an infrastructure for run-time reconfigurable (RTR) modules.
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    • "In literature, the most relevant attempts to realize a bus– based system for reconfigurable architectures are RMBoC [6], [7] and BUS–COM [8]; the former (Reconfigurable Multiple Bus–on–Chip) has bus segments connecting hop–by–hop the modules interface, while the latter uses a centralized set of buses with an arbiter granting access to the communication medium in time–division multiplexing. The two approaches are reported in Figure 2. "
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    ABSTRACT: On-chip communication design is a complex task, since the communication requirements and the complexity of the target application are high. With the introduction of dynamic reconfiguration (a feature than can be found, for instance, in recent Field Programmable Gate Arrays), the design of a reconfigurable communication infrastructure becomes a suitable approach to increase both the flexibility and the adaptability of such a system. These are two of the key features of a communication infrastructure for reconfigurable systems, since usually the designer is not aware of which will be the executing modules and the communication requirements at run-time. This paper introduces and describes a novel reconfigurable communication infrastructure for dynamically reconfigurable architectures. The proposed approach is a tile-based network-on-chip in which the communication layer is completely decoupled from the computational one. The proposed approach is designed to support dynamic reconfiguration at the communication fabrics level.
    Proceedings of the 2008 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2008), Samos, Greece, July 21-24, 2008; 01/2008
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    • "Mak et al. [7] presents a taxonomy of on-FPGA communication architectures with representative examples. Pionteck et al. [8] also gives an overview of several architectures specific to dynamic reconfiguration. Most closely related to this work is DIMEtalk [14], a tool that configures a communication network within an FPGA system. "
    Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA 2008, Las Vegas, Nevada, USA, July 14-17, 2008; 01/2008
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