# Double patterning layout decomposition for simultaneous conflict and stitch minimization.

**ABSTRACT** Double patterning lithography (DPL) is considered as a most likely solution for 32 nm/22 nm technology. In DPL, the layout patterns are decomposed into two masks (colors), and manufactured through two exposures and etch steps. If the spacing between two features (polygons) is less than certain minimum coloring distance, they have to be assigned opposite colors. However, a proper coloring is not always feasible because two neighboring patterns within the minimum distance may be in the same mask due to complex pattern configurations. In that case, a feature may need to be split into two parts to resolve the conflict, resulting in stitch insertion which causes yield loss due to overlay and line-end effect. While previous layout decomposition approaches perform coloring and splitting separately, in this paper, we propose a simultaneous conflict and stitch minimization algorithm with an integer linear programming (ILP) formulation. Since ILP is in class NP-hard, the algorithm includes three speed-up techniques: 1) grid merging; 2) independent component computation; and 3) layout partition. In addition, our algorithm can be extended to handle design rules such as overlap margin and minimum width for practical use as well as off-grid layout. Our approach can reduce 33% of stitches and remove conflicts by 87.6% compared with two phase greedy decomposition. Index Terms—Double patterning lithography, integer linear programming, layout decomposition.

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**ABSTRACT:**For 32/22 nm technology nodes and below, double patterning (DP) lithography has become the most promising interim solutions due to the delay in the deployment of next generation lithography (e.g., EUV). DP requires the partitioning of the layout patterns into two different masks, a procedure called layout decomposition. Layout decomposition is a key computational step that is necessary for double patterning technology. Existing works on layout decomposition are all single-threaded, which is not scalable in runtime and/or memory for large industrial layouts. This paper presents the first window-based parallel layout decomposition methods for improving both runtime and memory consumption. Experimental results are promising and show the presented parallel layout decomposition methods obtain upto 21× speedup in runtime and upto 7.5×reduction in peak memory consumption with acceptable solution quality.Integration the VLSI Journal 01/2013; · 0.41 Impact Factor -
##### Conference Paper: Role of design in multiple patterning: Technology development, design enablement and process control

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**ABSTRACT:**Multiple-patterning optical lithography is inevitable for technology scaling beyond the 22nm technology node. Multiple patterning imposes several counter-intuitive restrictions on layout and carries serious challenges for design methodology. This paper examines the role of design at different stages of the development and adoption of multiple patterning: technology development, design enablement, and process control. We discuss how explicit design involvement can enable timely adoption of multi-patterning with reduced costs both in design and manufacturing.Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013; 01/2013 - [Show abstract] [Hide abstract]

**ABSTRACT:**Triple Patterning Lithography (TPL) is widely recognized as a promising solution for 14/10nm technology node. In this paper, we propose an efficient layout decomposition approach for TPL, with the objective to minimize the number of conflicts and stitches. Based on our analysis of actual benchmarks, we found that the whole layout can be reduced into several types of small feature clusters, by some simplification methods, and the small clusters can be solved very efficiently. We also present a new stitch finding algorithm to find all possible legal stitch positions in TPL. Experimental results show that the proposed approach is very effective in practice, which can achieve significant reduction of manufacturing cost, compared to the previous work.Design Automation Conference (DAC), 2013 50th ACM / EDAC / IEEE; 01/2013

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 29, NO. 2, FEBRUARY 2010185

Double Patterning Layout Decomposition for

Simultaneous Conflict and Stitch Minimization

Kun Yuan, Jae-Seok Yang, and David Z. Pan, Senior Member, IEEE

Abstract—Double patterning lithography (DPL) is considered

as a most likely solution for 32nm/22nm technology. In DPL,

the layout patterns are decomposed into two masks (colors),

and manufactured through two exposures and etch steps. If

the spacing between two features (polygons) is less than certain

minimum coloring distance, they have to be assigned opposite

colors. However, a proper coloring is not always feasible because

two neighboring patterns within the minimum distance may be

in the same mask due to complex pattern configurations. In that

case, a feature may need to be split into two parts to resolve the

conflict, resulting in stitch insertion which causes yield loss due to

overlay and line-end effect. While previous layout decomposition

approaches perform coloring and splitting separately, in this

paper, we propose a simultaneous conflict and stitch minimization

algorithm with an integer linear programming (ILP) formulation.

Since ILP is in class NP-hard, the algorithm includes three

speed-up techniques: 1) grid merging; 2) independent component

computation; and 3) layout partition. In addition, our algorithm

can be extended to handle design rules such as overlap margin

and minimum width for practical use as well as off-grid layout.

Our approach can reduce 33% of stitches and remove conflicts

by 87.6% compared with two phase greedy decomposition.

Index Terms—Double patterning lithography, integer linear

programming, layout decomposition.

I. Introduction

A

due to the delay of the next generation lithography equipment

such as extreme ultraviolet [1]. Double patterning lithogra-

phy (DPL) [2]–[5] emerges almost the only alternative for

32nm/22nm nodes and it is already used for NAND-flash

production. In DPL, a single layout is decomposed into two

masks and manufactured through two exposure/etching steps.

As a benefit, the pitch size is doubled, which enhances the

resolution as illustrated in Fig. 1. Although DPL requires two

masks and increases the design cost, it is widely considered

as a most likely solution for 32nm, 22nm, and even 16nm.

Double patterning layout decomposition [6]–[8] is a process

that assigns two features within the given minimum space

S the minimum feature size decreases, semiconductor

industry is facing the limitation of patterning sub-32nm

Manuscript received June 9, 2009; revised August 17, 2009. Current version

published January 22, 2010. This paper was supported in part by the National

Science Foundation, Semiconductor Research Corporation, Sun, Qualcomm,

and equipment donations from Intel. This paper was recommended by

Associate Editor P. Saxena.

The authors are with the Department of Electrical and Computer

Engineering, University of Texas, Austin, TX 78731 USA (e-mail:

kyuan@cerc.utexas.edu; jsyang@cerc.utexas.edu; dpan@cerc.utexas.edu).

Color versions of one or more of the figures in this paper are available

online at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TCAD.2009.2035577

Fig. 1.

is increased effectively in DPL.

One single design is decomposed into two masks and the pitch size

to different masks. A layout may contain a pattern which

is unable to assign a color. In this case, a feature may be

split into two parts and colored differently to resolve the

conflict, which generates stitches. Stitches will cause yield

loss and increase manufacturing cost due to overlay errors,

which is 5nm or 6nm under current 32nm double patterning

lithography. Some mask misalignment direction [4] could be

actually beneficial for printability. However, on the presence of

various process uncertainties, such as dose, focus, and mask

errors, the printed stitch width could be easily smaller than

25nm and result in design failure. Pushing overlay below

3nm [9] is very challenging. Moreover, the additional line-

ends may cause more pattern degradation and reduce yield

in case of defocus and dose variation. After splitting, a few

unresolved or even unresolvable conflicts may remain and will

be corrected by time consuming layout redesign. Therefore, it

is important to produce high quality decomposition solution

with less conflicts and stitches.

There are a few works focusing on stand-alone layout

decomposition. A heuristic approach is proposed in [7] to

cut troublesome patterns after finding the coloring conflicts.

The patterns are prefragmented into smaller pieces in [8] to

perform coloring. All these works do not have a systematical

way to minimize the number of conflicts and stitches. Coloring

and splitting are considered in separate steps while they are

highly correlated tasks. Pattern matching technique is proposed

in [10] to decompose the layout. However, it might not be

able to work on large scale problem, hence limits the solution

quality. Recently, a practical layout decomposition flow is

proposed in [11] to address design needs for double patterning.

They first detect the features associated with unresolvable

conflict cycles for layout modification. The remaining design

is then decomposed to minimize the number of stitches based

on an ILP formulation. However, in their work, the number

of unresolvable conflict cycles and splitting stitches are not

optimized together, and conflict elimination technique is quite

greedy.

0278-0070/$26.00 c ? 2010 IEEE

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186IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 29, NO. 2, FEBRUARY 2010

Fig. 2. Concept of conflict and stitch.

In this paper, we propose an algorithm to decompose layout

for minimizing conflicts and stitches simultaneously. The

proposed approach reduces the conflicts by 87.6% with 33%

less stitches compared to a greedy two phase decomposition

flow. When compared to a methodology based on [11], we are

also able to achieve averagely 87.2% and 10% reduction on

conflicts and stitches, respectively. Although our approach is

comparatively slower, we can obtain coloring solutions for all

the test cases within a few minutes. The runtime shows linear

complexity with respect to problem size.

Our main contributions are as follows.

1) We propose a new grid model to enable bigger solution

space than previous works [7], [8] and perform simul-

taneous conflict and stitch optimization.

2) We develop an ILP algorithm to minimize the number

of conflicts and stitches for a high quality solution.

3) We propose three speed-up techniques (grid merging,

independent component computing and layout partition)

to improve the runtime and scalability of our algorithm.

For layout partition, we identify and solve a coloring

flip optimization problem to minimize the conflicts and

stitches across the boundary of different partitions.

4) We discuss how to extend our proposed grid model

to handle various splitting rules and design patterns in

practice.

The rest of the paper is organized as follows. Section II

provides the preliminaries and motivates. In Section III, we

discuss the problem formulation with related model and defi-

nitions. The basic ILP formulation is described in Section IV

with three speed-up techniques. The extensive discussion

on grid model for practical design issues is presented in

Section V. Section VI presents the experiment results and

Section VII concludes this paper.

II. Preliminaries and Motivation

A. Double Patterning Layout Decomposition Considerations

As explained in Section I, in DPL, the original design will

be assigned into two masks. There are two critical issues with

this layout decomposition: coloring conflict and splitting stitch.

1) Coloring Conflict: If the distance between two separate

features is less than minimum coloring spacing mincs, they

Fig. 3.

works [7], [8]. An unplanned coloring will need much extra effort during

splitting.

Shortcoming of two phase layout decomposition flow in previous

should be assigned to different masks (colors). Otherwise,

there will be a coloring conflict.

Fig. 2(a) shows a layout with three features, and any two

of them are required to have different colors because of the

insufficient spacing. A coloring conflict will be unavoidable

as in Fig. 2(b). Sometimes, such a violation can be eliminated

by appropriately splitting the features like Fig. 2(c). There

are also unresolvable conflicts, as Fig. 2(d) indicates, which

requires modifying the design.

2)

Splitting Stitch: The stitch exists when two touched

features are assigned to different masks. The stitch can be

inserted to split some features to resolve the conflict as shown

in Fig. 2(c). However, stitch insertion can have negative effects

on yield due to overlay error between the two masks as

Fig. 2(e) illustrates. In addition, the line-end will cause pattern

degradation.

There are several practical guidelines for splitting. As

Fig. 2(f) shows, in order to control the overlay, there is a

minimum overlap length, minol, requirement for stitch inser-

tion. The segments h1 and h2 on different masks should be

overlapped to certain amount ensuring better manufacturabil-

ity. Moreover, we do not want to have any minimum width,

minwi, rule violation during splitting, as marked by the circle

in Fig. 2(f).

Without altering layout in the scope, the general objective

of layout decomposition can be stated as minimizing the

unresolved conflicts by introducing as few as possible stitches.

B. Simultaneous Optimization

The previous works insert stitches after coloring to resolve

conflicts. Without planning possible splitting during coloring,

it is hard to eliminate the conflict. Considering a layout in

Fig. 3(a), we have a coloring solution in Fig. 3(b). During

the splitting, the U feature should be cut into two parts to

remove the conflict but we have to further check whether

the splitting will result in another conflict like Fig. 3(c). In

such case, the coloring of the neighborhood features needs to

be reconsidered to avoid unnecessary stitches like Fig. 3(d)

and enable optimal solution in Fig. 3(e) or (f). This is a

simple example, but as we can see, given the complexity

of modern design, the two-phase approach will have extreme

difficulty handling the exploding consideration and producing

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YUAN ET AL.: DOUBLE PATTERNING LAYOUT DECOMPOSITION FOR SIMULTANEOUS CONFLICT AND STITCH MINIMIZATION187

Fig. 4. Different stitch candidates can lead to different solution qualities.

Fig. 5. Difficulty of predicting where the splitting is needed.

high quality solution. This motivates us simultaneous conflict

and stitch minimization during layout decomposition.

III. Problem Formulation

In this section, we will first motivate and introduce our grid

model in Section III-A. The basic terms will be defined in the

following Section III-B. The formal problem definition will be

described in the end.

A. Grid Layout Model

Considering splitting during coloring is a challenging prob-

lem. First of all, the stitch configurations are highly correlated

and all the potential locations need to be considered for global

optimality. Fig. 4(a) is a case with two conflicts. As we can see,

two possible splitting choices on feature A lead to two different

solutions, Fig. 4(b) and (c). The first one has two stitches,

where the latter one associates with only one. Moreover, we

can even hardly predict where we could have a splitting due

to some chain effect. For example, the right most feature D is

not expected to be cut in Fig. 5(a) because it is only adjacent

to one single feature A. However, given a coloring assignment

as shown in Fig. 5(b), feature A will be split to resolve the

conflict between A and B like Fig. 5(c). As a result, feature

D also needs to be broken into two segments as shown in

Fig. 5(d).

In order to overcome these issues, we will map the whole

layout into grids with its size to be half the pitch of the

original design. Each grid is either empty or fully occupied

by the pattern, and each occupied grid will be assigned one

color. Therefore, any boundary between grids is a potential

splitting location. This is shown in the Fig. 6. Essentially, we

provide fine resolution for splitting options. This model is able

to offer sufficient stitch candidates for all the features across

the design in practice and the solution space is much bigger

than previous works [7], [8]. The discretization is reasonable

because a design usually follows underlying regular pitches

Fig. 6. Proposed grid layout model.

Fig. 7.

box.

Concept of blocking path. The solid rectangle marks the bounding

in modern layout. Minimum coloring spacing mincsis taken

as two-grid size to double the spacing for each mask in this

paper and also subject to change according to given mincs.

B. Terms and Problem Formulation

Before formulating our problem, we will first define the

terms in the grid layout model.

Definition 1 (Occupied Grid, OG): The grid filled by the

layout.

The OG must be assigned one of the two colors: gray and

black.

Definition 2 (Blocking Path, BP): Given two occupied grids

OG1and OG2, a blocking path is a path when:

1) it is fully composed of OGs and connects OG1 and

OG2;

2) OG1 and OG2 are touching its two ending grids, re-

spectively, but not belonging to this path;

3) this path is within the bounding box of OG1and OG2.

The main usage of blocking path is to identify neighboring

but locally isolated layout grids. These grids, even belonging

to the same connection, need to be considered as different

features, and could form a coloring conflict.

As shown in Fig. 7(a), C–D is a blocking path for grid A

and B. In another example Fig. 7(b), C–F is not a BP for A–B,

because not all of them are in the bounding box of A–B as the

third rule defines. Some part of it (C–E) is beyond the box,

and hence locally A–B can be considered as isolated.

Definition 3 (Potential Conflict Grid Pair, PCGP, and

Potential Stitch Grid Pair, PSGP): Given two occupied grids

OG1and OG2.

1) If the distance between OG1and OG2is less than mincs

and the two grids are not touching, they form a potential

conflict grid pair.

2) If OG1 and OG2 are touching, they form a potential

stitch grid pair.

The distance between a pair of OGs is the minimum

distance between any two points from the OGs. For example

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188IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 29, NO. 2, FEBRUARY 2010

Fig. 8.

the bounding box of A and B.

Stitch grid pair and conflict grid pair. Dashed box in (c) and (d) is

in Fig. 7(b), the distance for untouched B and C is

size due to two closest corners, which is smaller than mincs.

Therefore, they form a PCGP.

Definition 4 (Stitch Grid Pair, SGP): If the grids of a PSGP

are assigned different colors, it is a stitch grid pair.

Definition 5 (Conflict Grid Pair, CGP):

the identical color, and there is no blocking path connecting

them in the same mask, it is a conflict grid pair.

The definition of SGP is straightforward as grids A and B

shown in Fig. 8(a). Fig. 8(b) shows the normal CGP cases,

where a PCGP is colored identically and unconnected. B–F

and A are within the minimum coloring spacing. There are

even no paths connecting them, not to mention blocking path.

The rule one of Definition 2 is violated. As a result, any of

B–F and A are a CGP.

There are also some special CGP cases that we need

to further consider blocking path in order to avoid false

recognition of lithography friendly pattern. If two nontouching

grids are electrically connected through a blocking path, we

should not consider them belonging to different features. The

printability will not be an issue. As shown in Fig. 8(c), grid

A and B have a BP C–D in the same mask between them,

so they do not form a CGP. It is indeed a normal jog, and

can be printed well. In contrast, although there is a path C–F

connecting A and B in Fig. 8(d), C–E is out of their bounding

box. In consequence, the path is not a blocking path. This

violates the third rule of Definition 2, so grid A and B form

a CGP. In this case, A and B are in fact locally isolated

but neighboring within the bounding box. This configuration

is a typical U shape pattern, and would have weak printa-

bility.

√2 grid

If a PCGP is in

C. Problem Description

In our work, we use the number of SGPs and CGPs

as the cost, which assigns higher weight to the grids that

are associated with more conflicts/stitches. Formally, we for-

mulate the layout decomposition optimization problem as

follows:

Problem Formulation: Given a grid layout, color it into two

parts (gray and black). The primary objective is to minimize

the number of CGPs and the second objective is to minimize

the number of SGPs.

We prefer a solution with less CGPs than one with smaller

number of SGPs but more CGPs, because a layout with

nonzero CGPs is essentially not manufacturable and a solution

with less CGPs reduces expensive redesign effort.

Fig. 9.Overall layout decomposition flow.

TABLE I

Notation for Basic ILP Formulation

ogi,j

xi,j

Occupied grid of which i and j are coordinates.

Binary variable that denotes the color of ogi,j.

xi,j= 1 if the color is gray, otherwise, it is black.

Binary variable sij,mn= 1 if ogi,jand

ogm,nis a SGP.

Binary variable cpq,uv= 1 if ogp,qand ogu,v

is a CGP.

Set of PSGPs.

Set of PCGPs.

Set of BPs connecting ogp,qand ogu,v.

kthBP connecting ogp,qand ogu,v.

Number of grids in pk

Binary variable gpq,uv= 1 if pk

is a gray BP.

Binary variable bpq,uv= 1 if pk

is a black BP.

sij,mn

cpq,uv

SP

CP

Ppq,uv

pk

pq,uv

nk

pq,uv

gk

pq,uv

pq,uv.

pq,uv

bk

pq,uvpq,uv

IV. Algorithm

In this section, we will present our ILP-based layout de-

composition algorithm. The entire flow is shown in Fig. 9.

After mapping the design to grid model, we will process

the grids and formulate the basic ILP formulation. Since the

timing complexity for ILP is very high, we will then propose

three speed-up techniques by either eliminating unnecessary

variables or dividing the whole problem into several smaller

ones. Finally, the layout decomposition for the entire design

can be obtained by merging the subproblem solutions. For

better solution reunion, we formulate a problem of coloring

flipping optimization through ILP.

A. Basic ILP Formulation

To better present our method, we first describe the notation

in Table I. The simultaneous coloring and splitting optimiza-

tion can be formulated as follows:

⎛

sij,mn∈SP

subject to

min

⎝

?

sij,mn+ α

?

cpq,uv∈CP

cpq,uv

⎞

⎠

(1)

xi,j+ (1 − xm,n) ≤ 1 + sij,mn

∀sij,mn∈ SP

(2)

(1 − xi,j) + xm,n≤ 1 + sij,mn

∀sij,mn∈ SP

(3)

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YUAN ET AL.: DOUBLE PATTERNING LAYOUT DECOMPOSITION FOR SIMULTANEOUS CONFLICT AND STITCH MINIMIZATION 189

?

?

?

xe,f∈pk

pq,uv

xe,f≤ (nk

pq,uv− 1) + gk

pq,uv

∀pk

pq,uv∈ Ppq,uv

(4)

xe,f∈pk

pq,uv

(1 − xe,f) ≤ nk

pq,uv(1 − gk

pq,uv)

∀pk

pq,uv∈ Ppq,uv

(5)

xe,f∈pk

pq,uv

(1 − xe,f) ≤ (nk

?

xp,q+ xu,v≤ 1 + cpq,uv+

pq,uv− 1) + bk

pq,uv

∀pk

pq,uv∈ Ppq,uv

(6)

xe,f∈pk

pq,uv

xe,f≤ nk

pq,uv(1 − bk

pq,uv)

∀pk

pq,uv∈ Ppq,uv

(7)

?

k

gk

pq,uv

∀cpq,uv∈ CP

(8)

(1 − xp,q) + (1 − xu,v) ≤ 1 + cpq,uv+

?

k

bk

pq,uv

∀cpq,uv∈ CP. (9)

The objective function (1) is to minimize the weighted

summation of SGPs and CGPs. Parameter α is used to tune

the relative importance between SGP and CGP, and can be set

to ensure the priority of CGP elimination. All the PCGPs and

PSGPs are predetermined by examining the neighboring grids

for each OG.

Constraints (2) and (3) are used to identify SGP from

PSGP. According to the definition of SGP, we need to know

whether the PSGP grids have opposite colors. Whenever xi,j

and xm,nhave opposite values, the left hand side of one of the

constraints will be two. As a result, sij,mn must be assigned

one to satisfy the constraints, which detects a SGP.

The usage of Constraints (4)–(9) is to determine whether

a PCGP forms a CGP. Identifying CGP takes more effort.

Besides checking the colors of PCGP, we need to know

whether there is a blocking path in the same mask. All the

possible BPs Ppq,uv can be easily enumerated by depth first

search on the occupied grids within the bounding box. We

can investigate their coloring using Constraints (4)–(7). The

corresponding binary variable gk

if the grids of some blocking path are in the same mask.

Constraints (8) and (9) evaluate the conditions for CGP. A

conflict will be reported only if PCGP grids are assigned same

color and the possible BPs gk

Let nogbe the number of occupied grids, the basic formu-

lation contains at most O(nog) variables. The constraints are

specified for detecting either PSGPs or PCGPs. Suppose there

are nspPSGPs and ncpPCGPs, the complexity of nspis O(nog).

ncpis linearly related to nog, but quadratically proportional to

mincs. The complexity of constraints due to PSGPs is O(nsp).

The constraint number for PCGPs is linear proportional to ncp.

It is also exponentially related to mincs, which results from

the enumeration of blocking paths. Although this formulation

shows exponential complexity in terms of mincs, when we fix

the value of mincsas the presetting for layout decomposition,

the number of variables and constraints is quadratic with

respect to nog.

The proposed integer linear formulation can minimize the

number of conflicts and stitches simultaneously. However,

because ILP is nondeterministic polynomial time-complete, it

is not affordable to directly apply a basic ILP formulation for

large modern designs.

pq,uv/bk

pq,uvwill be true only

pq,uv/bk

pq,uvdo not exist.

Fig. 10. Main idea of grid merging.

Fig. 11.

having no interacted PSGPs/PCGPs and marked by the dashed circle.

Example of breaking big layout into two independent components,

B. Speed-Up Techniques

In this section, we will discuss three speed-up techniques.

The clustering methodology is applied in grid merging to

reduce the number of variables and constraints. In contrast,

the key idea of the other two techniques is to use a divide

and conquer algorithm to convert the problem into smaller

subproblems.

1) Grid Merging: In the proposed grid model, we aim to

provide very fine resolution for stitch candidates. This may be

over skilled under certain situations.

Consider the layout segment L in Fig. 10(a) with unit grids

A–B–C–D. Only the two ending grids A and D may have

coloring interaction with other layout objects besides L. B and

C can be considered as isolated to some extent, because there

are no occupied grids outside A–B–C–D which are touching

them or within mincs of their boundary. Therefore, it is not

possible for B or C to form a stitch or conflict with other

layout apart from the grids of segment L.

We can make advantage of above property to reduce prob-

lem size by combining this type of connected grids into a big

super grid. As graphically shown in Fig. 10(b), B and C can

be treated as a united grid T. This is equivalent to enforce B

and C the same color. It will not deteriorate the conflict and

stitch optimization. For this super grid, it does not have any

chance to form a conflict or stitch with surrounding grids other

than its two adjacent grids A and D.

Generally speaking, the elimination of internal splitting

candidates is not a problem for solution quality. For any

optimized solution obtained under original grid model with

internal stitches, it can be mapped to one solution in the

merged model with the stitch propagated to its ending grids,

such as from (c) to (d) in Fig. 10.

2)

Independent Component Computation: We propose

independent component computation for reducing the ILP

problem size without losing optimality. In real layout, we

observe many isolated occupied grid clusters, i.e., there are

no PSGPs or PCGPs formed between them. Therefore, we can