Double patterning layout decomposition for simultaneous conflict and stitch minimization.
ABSTRACT Double patterning lithography (DPL) is considered as a most likely solution for 32 nm/22 nm technology. In DPL, the layout patterns are decomposed into two masks (colors), and manufactured through two exposures and etch steps. If the spacing between two features (polygons) is less than certain minimum coloring distance, they have to be assigned opposite colors. However, a proper coloring is not always feasible because two neighboring patterns within the minimum distance may be in the same mask due to complex pattern configurations. In that case, a feature may need to be split into two parts to resolve the conflict, resulting in stitch insertion which causes yield loss due to overlay and line-end effect. While previous layout decomposition approaches perform coloring and splitting separately, in this paper, we propose a simultaneous conflict and stitch minimization algorithm with an integer linear programming (ILP) formulation. Since ILP is in class NP-hard, the algorithm includes three speed-up techniques: 1) grid merging; 2) independent component computation; and 3) layout partition. In addition, our algorithm can be extended to handle design rules such as overlap margin and minimum width for practical use as well as off-grid layout. Our approach can reduce 33% of stitches and remove conflicts by 87.6% compared with two phase greedy decomposition. Index Terms—Double patterning lithography, integer linear programming, layout decomposition.
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Conference Proceeding: Key directions and a roadmap for electrical design for manufacturability[show abstract] [hide abstract]
ABSTRACT: Semiconductor product value increasingly depends on "equivalent scaling" achieved by design and design-for-manufacturability (DFM) techniques. This talk addresses trends and a roadmap for "equivalent scaling" innovation at the design-manufacturing interface. The first part will discuss precepts of electrical DFM. What are dominant aspects of manufacturing variability and design requirements? Can designs match process, or must process inevitably adapt to designs? In what sense can concepts of "virtual manufacturing" or "statistical optimization" succeed in the design flow? How should design technology balance analyses that preserve value, versus optimizations that extend value? How should we balance preventions (correct by construction), versus early interventions, versus cures (construct by correction), versus "do no harm" opportunism? Or, tools that can model and predict well, versus tools that can make upstream assumptions come true? The second part will give a roadmap for electrical DFM technologies, motivated by emerging challenges (stress/strain engineering, mask errors, double-patterning lithography, etc.) and highlighting needs for < 45 nm nodes.37th European Solid State Device Research Conference, 2007. ESSDERC; 10/2007
Conference Proceeding: Layout decomposition for double patterning lithography.[show abstract] [hide abstract]
ABSTRACT: In double patterning lithography (DPL) layout decomposition for 45nm and below process nodes, two features must be assigned opposite colors (corresponding to different exposures) if their spacing is less than the minimum coloring spacing [11, 9, 5]. However, there exist pattern configurations for which pattern features separated by less than the minimum color spacing cannot be assigned different colors. In such cases, DPL requires that a layout feature be split into two parts. We address this problem using a layout decomposition algorithm that includes graph construction, conflict cycle detection, and node splitting processes. We evaluate our technique on both real-world and artificially generated testcases in 45nm technology. Experimental results show that our proposed layout decomposition method effectively decomposes given layouts to satisfy the key goals of minimized line-ends and maximized overlap margin. There are no design rule violations in the final decomposed layout.2008 International Conference on Computer-Aided Design (ICCAD'08), November 10-13, 2008, San Jose, CA, USA; 01/2008