Conference Paper

Double patterning layout decomposition for simultaneous conflict and stitch minimization.

Dept. of Electr. & Comput. Eng., Univ. of Texas, Austin, TX, USA
DOI: 10.1145/1514932.1514958 Conference: Proceedings of the 2009 International Symposium on Physical Design, ISPD 2009, San Diego, California, USA, March 29 - April 1, 2009
Source: DBLP

ABSTRACT Double patterning lithography (DPL) is considered as a most likely solution for 32 nm/22 nm technology. In DPL, the layout patterns are decomposed into two masks (colors), and manufactured through two exposures and etch steps. If the spacing between two features (polygons) is less than certain minimum coloring distance, they have to be assigned opposite colors. However, a proper coloring is not always feasible because two neighboring patterns within the minimum distance may be in the same mask due to complex pattern configurations. In that case, a feature may need to be split into two parts to resolve the conflict, resulting in stitch insertion which causes yield loss due to overlay and line-end effect. While previous layout decomposition approaches perform coloring and splitting separately, in this paper, we propose a simultaneous conflict and stitch minimization algorithm with an integer linear programming (ILP) formulation. Since ILP is in class NP-hard, the algorithm includes three speed-up techniques: 1) grid merging; 2) independent component computation; and 3) layout partition. In addition, our algorithm can be extended to handle design rules such as overlap margin and minimum width for practical use as well as off-grid layout. Our approach can reduce 33% of stitches and remove conflicts by 87.6% compared with two phase greedy decomposition. Index Terms—Double patterning lithography, integer linear programming, layout decomposition.

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    • "Given input layout which is specified by features in polygonal shapes, a decomposition graphs [4] [5] is constructed by Definition 1. "
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    ABSTRACT: For next-generation technology nodes, multiple patterning lithography (MPL) has emerged as a key solution, e.g., triple patterning lithography (TPL) for 14/11nm, and quadruple patterning lithography (QPL) for sub-10nm. In this paper, we propose a generic and robust layout decomposition framework for QPL, which can be further extended to handle any general K-patterning lithography (K$>$4). Our framework is based on the semidefinite programming (SDP) formulation with novel coloring encoding. Meanwhile, we propose fast yet effective coloring assignment and achieve significant speedup. To our best knowledge, this is the first work on the general multiple patterning lithography layout decomposition.
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    • "It suggests performing the TP layout decomposition by solving an integer linear program (ILP), which minimizes coloring conflicts as well as stitches. Solving the coloring problem with an ILP was shown to reach good solutions for DP [3] [4] [5] and the extension for TP is likely to reach good solutions for the 3-coloring problem as well. For design-level layout decomposition with large designs, solving the ILP is impractical because it requires a very long run-time. "
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    ABSTRACT: Double patterning (DP) in a litho-etch-litho-etch (LELE) process is an attractive technique to scale the K1 factor below 0.25. For dense bidirectional layers such as the first metal layer (M1), however, density scaling with LELE suffers from poor tip-to-tip (T2T) and tip-to-side (T2S) spacing. As a result, triple-patterning (TP) in a LELELE process has emerged as a strong alternative. Because of the use of a third exposure/etch, LELELE can achieve good T2T and T2S scaling as well as improved pitch scaling over LELE in case further scaling is needed. TP layout decomposition, a.k.a. TP coloring, is much more challenging than DP layout decomposition. One of the biggest complexities of TP decomposition is that a stitch can be between different two-mask combinations (i.e. first/second, first/third, second/third) and, consequently, stitches are color-dependent and candidate stitch locations can be determined only during/after coloring. In this paper, we offer a novel methodology for TP layout decomposition. Rather than simplifying the TP stitching problem by using DP candidate stitches only (as in previous works), the methodology leverages TP stitching capability by considering additional candidate stitch locations to give coloring higher flexibility to resolve decomposition conflicts. To deal with TP coloring complexity, the methodology employs multiple DP coloring steps, which leverages existing infrastructure developed for DP layout decomposition. The method was used to decompose bidirectional M1 and M2 layouts at 45nm, 32nm, 22nm, and 14nm nodes. For reasonably dense layouts, the method achieves coloring solutions with no conflicts (or a reasonable number of conflicts solvable with manual legalization). For very dense and irregular M1 layouts, however, the method was unable to reach a conflict-free solution and a large number of conflicts was observed. Hence, layout simplifications for the M1 layer may be unavoidable to enable TP for the M1 layer. Although we apply the method for TP, the method is more general and can be applied for multiple patterning with any number of masks.
    Proceedings of SPIE - The International Society for Optical Engineering 03/2012; DOI:10.1117/12.916636 · 0.20 Impact Factor
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    • "A. Prior art in DP coloring and conflict removal DP coloring has been the subject of extensive research [4] [5] [6] [7] [8] in recent years, while little work has been done on MP coloring and these will be discussed later on in Section II. Prior works in DP coloring [6] [7] [8] still suffer from some limitations, however. One limitation common to all previous works is that they perform segmentation of the layout into rectangles prior to the coloring and this segmentation has many drawbacks. "
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    ABSTRACT: The use of multiple patterning optical lithography for sub-20nm technologies has become inevitable with delays in adopting the next generation of lithography systems. The biggest technical challenge of multiple patterning is failure to reach a manufacturable layout-coloring solution, especially in dense layouts. This paper offers a post-layout solution for the removal of conflicts, i.e., patterns that cannot be colored without violations. The proposed method consists of three steps essentially: layout coloring, exposure layers and geometric rules definition, and, finally, layout legalization using compaction and multiple-patterning rules as constraints. The method is general and can be used for different multiple-patterning technologies including LELE double-patterning (DP), tripe/multiple-patterning (i.e., multiple litho-etch steps), and self-aligned double patterning (SADP). For demonstration purposes, we apply the proposed method in this paper to remove conflicts in DP. We offer an O(n) layout-coloring algorithm for DP, which is up to 200X faster than the ILP-based approach, and extend it for multiple-patterning (MP). The conflict-removal problem is formulated as a linear program (LP), which permits an extremely fast run-time (less than 1 minute in real time for macro layout). The method was tested on cells from a commercial 22nm library designed without any multiple-patterning awareness; for many cells, the method removes all conflicts without any area increase; for some complex cells, the method still removes all conflicts but with a modest 6.7% average increase in area.
    IC Design & Technology (ICICDT), 2012 IEEE International Conference on; 01/2012
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