Double patterning layout decomposition for simultaneous conflict and stitch minimization.
ABSTRACT Double patterning lithography (DPL) is considered as a most likely solution for 32 nm/22 nm technology. In DPL, the layout patterns are decomposed into two masks (colors), and manufactured through two exposures and etch steps. If the spacing between two features (polygons) is less than certain minimum coloring distance, they have to be assigned opposite colors. However, a proper coloring is not always feasible because two neighboring patterns within the minimum distance may be in the same mask due to complex pattern configurations. In that case, a feature may need to be split into two parts to resolve the conflict, resulting in stitch insertion which causes yield loss due to overlay and line-end effect. While previous layout decomposition approaches perform coloring and splitting separately, in this paper, we propose a simultaneous conflict and stitch minimization algorithm with an integer linear programming (ILP) formulation. Since ILP is in class NP-hard, the algorithm includes three speed-up techniques: 1) grid merging; 2) independent component computation; and 3) layout partition. In addition, our algorithm can be extended to handle design rules such as overlap margin and minimum width for practical use as well as off-grid layout. Our approach can reduce 33% of stitches and remove conflicts by 87.6% compared with two phase greedy decomposition. Index Terms—Double patterning lithography, integer linear programming, layout decomposition.
Conference Paper: Double patterning-aware detailed routing with mask usage balancing[Show abstract] [Hide abstract]
ABSTRACT: Double patterning lithography (DPL) for 32nm and 22nm technology nodes requires decomposing a layout into two masks for lithography. It is important to consider DPL during the detailed routing stage so that the layout can be decomposed easily with the minimum number of stitches. In this paper, we propose a double patterning-aware detailed routing algorithm to balance the mask usage. Different from previous works, we first fix the color of each track in the routing grid and perform detailed routing using these pre-colored tracks. Experimental results demonstrate that our algorithm yields a significant improvement on the number of stitches and decomposability.2014 15th International Symposium on Quality Electronic Design (ISQED); 03/2014
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ABSTRACT: Design rule is an important interface between design and manufacturing. It becomes more complex as the process advances to 16-nm and beyond. Current approaches to generate design rules are empirical shrink and lithographic simulation. However, it is time-consuming and costly to revise design rules for performance boost and yield improvement after design rules are frozen. Early performance gains in early design rule development without cost increase and yield loss will benefit semiconductor industry. In this work, we for the first time consider 16-nm bulk FinFET standard cell performance, yield, area, and layout style simultaneously to optimize design rules to meet ITRS by using geometric programming. Optical proximity correction, and electromagnetic field and circuit simulations are performed for objective function evaluation. The result achieves more than 100%-delay and 50%-yield improvement without area change by this systematic and statistical approach.2014 International Workshop on Computational Electronics (IWCE); 06/2014