Reap what you sow: spare cells for post-silicon metal fix.
ABSTRACT Post-silicon validation has recently become a major bottleneck in IC design. Several high prole IC designs have been taped-out with latent bugs, and forced the manufacturers to resort to addi- tional design revisions. Such changes can be applied through metal x; however, this is impractical without carefully pre-placed spare cells. In this work we perform the rst comprehensive analysis of the issues related to spare-cell insertion, including the types of spare cells that should be used as well as their placement. In ad- dition, we propose a new technique to measure the heterogeneity among signals and use it to determine spare-cell density. Finally, we integrate our ndings into a novel multi-faceted approach that calculates regional demand for spare cells, identies the most ap- propriate cell types, and places such cells into the layout. Our ap- proach enables the use of metal x at a much smaller delay cost, with a reduction of up to 37% compared to previous solutions.
Conference Proceeding: An ECO algorithm for resolving OPC and coupling capacitance violations[show abstract] [hide abstract]
ABSTRACT: In the deep submicron manufacturing (DSM) era, lithography/yield and noise are critical issues to be considered. Optical proximity correction (OPC) is becoming a key compensate technique for the light diffraction effect in lithography. Both OPC effect and the capacitive coupling on some wire segments can only be analyzed post routing in late design stage or post-silicon stepping design change. ECO (engineering change orders) is used in late design stage to fix violations that exceed the given OPC and coupling capacitance thresholds derived from analysis. These violations must be corrected in order to guarantee performance and yield. In this paper, we propose the first ECO routing algorithm which eliminates both OPC and coupling capacitance violations for wires. At the same time, the ECO routing obeys the given constraints so as to keep the new routing solution close to the existing one to preserve design timing and layout convergenceASIC, 2005. ASICON 2005. 6th International Conference On; 11/2005
Conference Proceeding: Automating post-silicon debugging and repair[show abstract] [hide abstract]
ABSTRACT: Modern IC designs have reached unparalleled levels of complexity, resulting in more and more bugs discovered after design tape-out However, so far only very few EDA tools for post-silicon debugging have been reported in the literature. In this work we develop a methodology and new algorithms to automate this debugging process. Key innovations in our technique include support for the physical constraints specific to post-silicon debugging and the ability to repair functional errors through subtle modifications of an existing layout. In addition, our proposed post-silicon debugging methodology (FogClear) can repair some electrical errors while preserving functional correctness. Thus, by automating this traditionally manual debugging process, our contributions promise to reduce engineers' debugging effort. As our empirical results show, we can automatically repair more than 70% of our benchmark designs.Computer-Aided Design, 2007. ICCAD 2007. IEEE/ACM International Conference on; 12/2007
Conference Proceeding: ECO timing optimization using spare cells[show abstract] [hide abstract]
ABSTRACT: We introduce in this paper a new problem of ECO timing optimization using spare-cell rewiring and present the first work for this problem. Spare-cell rewiring is a popular technique for incremental timing optimization and/or functional change after the placement stage. The spare-cell rewiring problem is very challenging because of its dynamic wiring cost nature for selecting a spare cell, while the existing related problems consider only static wiring cost. For the addressed problem, we present a framework of buffer insertion and gate sizing to handle it. In this framework, we present a dynamic programming algorithm considering the dynamic cost, called dynamic cost programming (DCP), for the ECO timing optimization with spare cells. Without loss of solution optimality, we further present an effective pruning method by selecting spare cells only inside an essential bounding polygon to reduce the solution space. The whole framework is integrated into a commercial design flow. Experimental results based on five industry benchmarks show that our method is very effective and efficient in fixing the timing violations of ECO paths.Computer-Aided Design, 2007. ICCAD 2007. IEEE/ACM International Conference on; 12/2007