Conference Paper

Reap what you sow: spare cells for post-silicon metal fix.

DOI: 10.1145/1353629.1353654 Conference: Proceedings of the 2008 International Symposium on Physical Design, ISPD 2008, Portland, Oregon, USA, April 13-16, 2008
Source: DBLP

ABSTRACT Post-silicon validation has recently become a major bottleneck in IC design. Several high prole IC designs have been taped-out with latent bugs, and forced the manufacturers to resort to addi- tional design revisions. Such changes can be applied through metal x; however, this is impractical without carefully pre-placed spare cells. In this work we perform the rst comprehensive analysis of the issues related to spare-cell insertion, including the types of spare cells that should be used as well as their placement. In ad- dition, we propose a new technique to measure the heterogeneity among signals and use it to determine spare-cell density. Finally, we integrate our ndings into a novel multi-faceted approach that calculates regional demand for spare cells, identies the most ap- propriate cell types, and places such cells into the layout. Our ap- proach enables the use of metal x at a much smaller delay cost, with a reduction of up to 37% compared to previous solutions.

Full-text

Available from: Igor L. Markov, May 28, 2015
0 Followers
 · 
113 Views
  • [Show abstract] [Hide abstract]
    ABSTRACT: This paper discusses design considerations of LC-based bandpass continuous-time ΣΔ modulators intended for the analog-to-digital conversion of radio-frequency signals in software-defined-radio receivers. A top-down high-level synthesis methodology - based on the combination of undersampling techniques, programmable notch frequency and adequate selection of loop-filter coefficients - is presented to design efficient modulator architectures, which can be adapted to fulfill the requirements of diverse wireless communication standards, while keeping stability and robustness to circuit errors. Main architectureand circuit-level design issues are analyzed, considering diverse case studies based on Gm-LC resonators and different kinds of digital-to-analog converters. Time-domain simulations validate the presented approach1.
    2014 IEEE International Symposium on Circuits and Systems (ISCAS); 06/2014
  • [Show abstract] [Hide abstract]
    ABSTRACT: Spare cells have been widely used to realize design changes at post-placement stage for functional changes or timing violations. However, many prior works relative to spare cell utilization neglect the timing effect due to spare cell rewiring. In this paper, the problem of timing-constrained cell replacement using spare cells is firstly formulated to consider the timing effect of the rewiring result. Furthermore, a three-phase approach is proposed to replace the changed cells in a combinational circuit with available spare cells while the timing constraints on the changed cells are satisfied. Experimental results show that our approach can efficiently realize the functional changes under the timing constraints for 5 tested cases.
    Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI; 05/2013
  • [Show abstract] [Hide abstract]
    ABSTRACT: To observe internal signals, physical probing is an important step in post-silicon debug. Focused ion beam (FIB) is one of most popular probing technologies. However, an unsuitable layout significantly decreases the percentage of nets which can be observed through FIB probing for advanced process technologies. This paper presents the first design-for-debug routing to increase the FIB observable rate. The proposed algorithm, which adopts three FIB states and costs to enhance the maze routing, keeps at least one FIB candidate for each net while routing. Experimental results demonstrate that the proposed method can significantly increase the FIB observable rate under 100% routability.
    Design Automation and Test in Europe; 01/2014