Conference Paper

Reap what you sow: spare cells for post-silicon metal fix.

DOI: 10.1145/1353629.1353654 Conference: Proceedings of the 2008 International Symposium on Physical Design, ISPD 2008, Portland, Oregon, USA, April 13-16, 2008
Source: DBLP


Post-silicon validation has recently become a major bottleneck in IC design. Several high prole IC designs have been taped-out with latent bugs, and forced the manufacturers to resort to addi- tional design revisions. Such changes can be applied through metal x; however, this is impractical without carefully pre-placed spare cells. In this work we perform the rst comprehensive analysis of the issues related to spare-cell insertion, including the types of spare cells that should be used as well as their placement. In ad- dition, we propose a new technique to measure the heterogeneity among signals and use it to determine spare-cell density. Finally, we integrate our ndings into a novel multi-faceted approach that calculates regional demand for spare cells, identies the most ap- propriate cell types, and places such cells into the layout. Our ap- proach enables the use of metal x at a much smaller delay cost, with a reduction of up to 37% compared to previous solutions.

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    • "ECO is then performed by rewiring the inputs and outputs of spare cells. Good metal-only ECO relies on the following four techniques (see Fig. 2). 1) Sufficient and evenly distributed spare cells: Spare cells should be uniformly spread over the whole design to accommodate sufficient resources for ECO at every possible location [3] and [4]. 2) A good ECO router: The rewiring of inputs and outputs is done by routing. "
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    ABSTRACT: To ease the time-to-market pressure and save the photomask cost, metal-only ECO realizes the last-minute design changes by revising the photomasks of metal layers only. This task is challenging because the pre-injected spare cells are limited in number and in cell types. Metal-only ECO has to implement these functional and/or timing changes using available spare cells. In this paper, we propose a stable matching based metal-only ECO synthesizer, named ECOS, that can implement the incremental design changes correctly without sacrificing timing and routability. The experiments are conducted on nine industrial testcases. These testcases reflect the real difficulties faced by designers and our results show that ECOS is promising for all of them.
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems 03/2012; 20(3):485-497. DOI:10.1109/TVLSI.2011.2104377 · 1.36 Impact Factor
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    • "In the second type, Chang et al. [7] proposed the effective approach to fix a number of errors by using a post-processing to shorten the manufactured time. Chang et al. [8] further explored the analysis-based method for spare cells selection and equally utilized the spare cells in the chip. Kuo et al. [9] synthesized the desired function by rewiring some interconnections for spare cells. "
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    ABSTRACT: This study formulates a novel routing problem of engineering change order- (ECO for short) aware Steiner minimal tree with obstacles and solves it by a multiple-stage approach, including partitioning, analysis distribution of spare cells, virtual node insertion and diagonal-based routing tree construction. The objective of this paper is to construct an ECO-aware routing tree in the sense of ECO resources. The number of available spare cells near the routing tree significantly increases while minimizing the additional length compared to the original tree algorithm. To efficiently analyze, an entire chip is divided into a set of fixed-size grids and the number of spare cells in each grid is calculated. To reduce the additional length, we insert the number of user-defined virtual nodes, which represent the grids with more spare cells. Furthermore, a graph-based routing algorithm is used to construct an X-architecture tree. To further reduce total wire length, each segment in the spanning tree is transferred into the corresponding combination of vertical, horizontal and diagonal segments. Experimental results show that the number of available spare cells is increases by 66.5%, while leading to only 2.8% additional total wire length.
    WSEAS Transactions on Circuits and Systems 09/2010; 9(9):567-576.
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    • "Particularly, IPR can be applied in post-silicon debugging (e.g. [24]) and engineering change order (ECO) for a quicker timing closure. The remaining of this paper is organized as follows. "
    Lei He · Yu Hu ·
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    ABSTRACT: As devices become smaller, circuits and systems are more vulnerable to soft errors caused by radiation and other environmental upsets. Fault tolerance measured by mean time to failure (MTTF) is desired, especially if no extra area, power and delay and little change of the existing design flow are introduced. Using FPGA as a testbed, this paper first presents fault tolerance techniques applying (1) logic don't care and path re-convergence (ROSE) and (2) in-place logic re-writing (IPR). Both increase MTTF by 2X with little or no overhead. Particularly, IPR does not change circuit placement and routing, and can be readily used with the existing industrial design flow. It also leads to a self evolution method to enhance fault tolerance for FPGA based circuits and systems. The ideas presented in the paper can be extend to handle regular logic fabrics, which are natural to nano-technologies and are also preferred by design for manufacturability (DFM) in scaled CMOS technologies.
    ASIC, 2009. ASICON '09. IEEE 8th International Conference on; 11/2009
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