Conference Paper

Fault Models and Injection Strategies in SystemC Specifications.

DOI: 10.1109/DSD.2008.35 Conference: 11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008
Source: DBLP

ABSTRACT This paper presents fault models and fault injection strategies designed in a simulation platform with reflection capabilities, used for simulating complex systems specified by using SystemC and by adopting a platform-based design approach. The approach allows the designer to work at different levels of abstraction and to take into account permanent and transient faults, and -- most important -- it features a transparent and dynamic mechanism for both injecting faults and analyzing the produced errors, in order to evaluate possible fault detection and/or tolerance design techniques.

0 Bookmarks
 · 
62 Views
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: The validation of fault-tolerance mechanisms in time-triggered dependable systems is usually carried out in the latest stages of the development process. As a consequence, fixing design faults found at late stages is very costly. Simulated Fault Injection (SFI) enables exercising the intended fault tolerance mechanisms by injecting faults in a simulated model of a system, which becomes a major benefit for designers since it reduces the risk of a late discovery of design flaws. This paper presents an integral modeling and simulation environment for dependable Time-Triggered HW/SW systems. Our approach facilitates the validation of fault-tolerance mechanisms by performing non-intrusive simulated fault injection on models of the system at different levels of abstraction, from the Platform Independent Model (PIM) to the Platform Specfic Model (PSM). We exemplify the feasibility of the proposed approach in a case study, where SFI is used to support the Failure Mode and Effect Analysis (FMEA) of an ETCS railway system based on the European Vital Computer (EVC).
    V Jornadas de ComputaciĆ³n Empotrada, Valladolid, Spain; 09/2014
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: This paper presents a testing and simulated fault injection framework for time-triggered safety-critical embedded systems. Our ap-proach facilitates the validation of fault-tolerance mechanisms by per-forming non-intrusive Simulated Fault Injection (SFI) on models of the system at different stages of the development, from the Platform Inde-pendent Model (PIM) to the Platform Specific Model (PSM). The SFI enables exercising the intended fault tolerance mechanisms by injecting faults in a simulated model of a system. The main benefit of this work is that it enables an early detection of design flaws in fault-tolerant sys-tems, what reduces the possibility of late discovery of design pitfalls that might require an expensive redesign of the system. We examine the fea-sibility of the proposed approach in a case study, where SFI is used to assess the fault tolerance mechanisms designed in a simplified railway signaling system.
    The 33rd International Conference on Computer Safety, Reliability and Security (SafeComp), Florence, Italy; 09/2014
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: The development and certification of safety critical embedded systems require the implementation of fault-tolerance mechanisms to ensure the safe operation of the system even in the presence of faults. These mechanisms need to be verified and validated by means of fault injection. Simulated fault injection enables an early dependability assessment that validates the correct implementation of fault-tolerance mechanisms and reduces the risk of late and expensive discovery of safety related pitfalls. This paper presents a novel modeling and simulation framework for time-triggered safety critical embedded systems. Our approach supports simulated fault injection at different abstraction levels (platform independent and platform specific models) and integrates a time-triggered automatic test executor for the early verification and validation of the systems. The feasibility of the proposed framework is illustrated with a case study where a simplified railway signaling system is modeled and simulated at different levels of abstraction.
    IEEE 17th International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC), Reno, USA; 06/2014