Conference Paper

Fault Models and Injection Strategies in SystemC Specifications

DOI: 10.1109/DSD.2008.35 Conference: 11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008
Source: DBLP


This paper presents fault models and fault injection strategies designed in a simulation platform with reflection capabilities, used for simulating complex systems specified by using SystemC and by adopting a platform-based design approach. The approach allows the designer to work at different levels of abstraction and to take into account permanent and transient faults, and -- most important -- it features a transparent and dynamic mechanism for both injecting faults and analyzing the produced errors, in order to evaluate possible fault detection and/or tolerance design techniques.

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    • "This corruption of the variable/signal values is performed using saboteurs. However, in contrast to other approaches ([16], [18]), our signal sabotaging technique is not intrusive, i.e., the fault injection activity is handled by the ATE and the models are not modified for the injection. For example, if the test case requires the corruption of a variable, the FIU reads the variable, performs the required fault injection (e.g. "
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    ABSTRACT: The validation of fault-tolerance mechanisms in time-triggered dependable systems is usually carried out in the latest stages of the development process. As a consequence, fixing design faults found at late stages is very costly. Simulated Fault Injection (SFI) enables exercising the intended fault tolerance mechanisms by injecting faults in a simulated model of a system, which becomes a major benefit for designers since it reduces the risk of a late discovery of design flaws. This paper presents an integral modeling and simulation environment for dependable Time-Triggered HW/SW systems. Our approach facilitates the validation of fault-tolerance mechanisms by performing non-intrusive simulated fault injection on models of the system at different levels of abstraction, from the Platform Independent Model (PIM) to the Platform Specfic Model (PSM). We exemplify the feasibility of the proposed approach in a case study, where SFI is used to support the Failure Mode and Effect Analysis (FMEA) of an ETCS railway system based on the European Vital Computer (EVC).
    V Jornadas de Computación Empotrada, Valladolid, Spain; 09/2014
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    • "SFI strategies and techniques have been widely analyzed in the past and several tools have been developed. Although most of them are focusing on VHDL models [18], [19], [20], SFI in SystemC models is getting an increasing interest in the latest years [21], [22], [23], given that SystemC is nowadays the de-facto standard in industrial HW/SW system co-design and simulation. "
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    ABSTRACT: The development and certification of safety critical embedded systems require the implementation of fault-tolerance mechanisms to ensure the safe operation of the system even in the presence of faults. These mechanisms need to be verified and validated by means of fault injection. Simulated fault injection enables an early dependability assessment that validates the correct implementation of fault-tolerance mechanisms and reduces the risk of late and expensive discovery of safety related pitfalls. This paper presents a novel modeling and simulation framework for time-triggered safety critical embedded systems. Our approach supports simulated fault injection at different abstraction levels (platform independent and platform specific models) and integrates a time-triggered automatic test executor for the early verification and validation of the systems. The feasibility of the proposed framework is illustrated with a case study where a simplified railway signaling system is modeled and simulated at different levels of abstraction.
    IEEE 17th International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC), Reno, USA; 06/2014
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    • "For example, in [11] a fault model is described for determining bit coverage information. The fault model for SystemC presented in [12] describes transient and permanent faults. These previous fault models cannot be used for describing bugs at the HDL level. "
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    ABSTRACT: A bottleneck during hardware design is the localization and the correction of faults — so-called debugging. Several approaches for automation of debugging have been proposed. This paper describes a methodology for evaluation and comparison of automated debugging algorithms. A fault model for faults occurring in SystemC descriptions at design time or during implementation is an essential part of this methodology. Each type of fault is characterized by mutations on the program dependence graph. The presented methodology is applied to evaluate the capability of a simulation based debugging procedure.
    Specification & Design Languages (FDL 2010), 2010 Forum on; 10/2010
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