Conference Paper

Efficient routing implementation in complex systems-on-chip.

Parallel Archit. Group, Univ. Politec. de Valencia, València, Spain
Conference: NOCS 2011, Fifth ACM/IEEE International Symposium on Networks-on-Chip, Pittsburgh, Pennsylvania, USA, May 1-4, 2011
Source: DBLP

ABSTRACT In application-specific SoCs, the irregularity of the topology ends up in a complex implementation of the routing algorithm, usually relying on routing tables implemented with memory structures. As system size increases, the routing table increases in size with non-negligible impact on power, area and latency overheads. In this paper we present a routing implementation for application-specific SoCs able to implement in an efficient manner (without requiring routing tables and using a small logic block in every switch) a routing algorithm in these irregular networks. The mechanism relies on a tool that maps the initial irregular topology of the SoC system into a logical regular structure where the mechanism can be applied. We provide details on the mapping tool as well the proposed routing mechanism. Evaluation results show the effectiveness of the mapping tool as well as the low area and timing requirements of the mechanism. With the mapping tool and the routing mechanism complex irregular SoC topologies can now be supported without the use of routing tables.

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    ABSTRACT: The availability of increased number of resources on a single silicon chip is enforcing the designers to come up with mechanisms for efficient and effective management of these resources on a chip. Moreover defective components, chip virtualization and power-aware techniques may lead to irregular on chip interconnection topology making efficient routing a non trivial challenge. Nearly, all routing algorithms and topologies support switches that make use of routing tables for efficient routing. However memories do not scale well in terms of area and power consumption for the routing tables, thus not practical for scalable on chip networks. Logic based distributed routing (LBDR) is recently proposed as an alternative solution to the table based distributed routing which can drastically reduce the memory requirement even while being as efficient as table based distributed routing. LBDR is a simple methodology of routing that enables the removal of the routing tables at every switch and uses only a small set of bits per switch to enable efficient routing. This paper surveys different variations of efficient Logic-based distributed routing (LBDR) proposed in the NoC research literature for regular and irregular on chip interconnection topologies.

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