Conference Paper

Efficient routing implementation in complex systems-on-chip.

Parallel Archit. Group, Univ. Politec. de Valencia, València, Spain
Conference: NOCS 2011, Fifth ACM/IEEE International Symposium on Networks-on-Chip, Pittsburgh, Pennsylvania, USA, May 1-4, 2011
Source: DBLP


In application-specific SoCs, the irregularity of the topology ends up in a complex implementation of the routing algorithm, usually relying on routing tables implemented with memory structures. As system size increases, the routing table increases in size with non-negligible impact on power, area and latency overheads. In this paper we present a routing implementation for application-specific SoCs able to implement in an efficient manner (without requiring routing tables and using a small logic block in every switch) a routing algorithm in these irregular networks. The mechanism relies on a tool that maps the initial irregular topology of the SoC system into a logical regular structure where the mechanism can be applied. We provide details on the mapping tool as well the proposed routing mechanism. Evaluation results show the effectiveness of the mapping tool as well as the low area and timing requirements of the mechanism. With the mapping tool and the routing mechanism complex irregular SoC topologies can now be supported without the use of routing tables.

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    • "LBDR approach is extended to LBDRx to cover complex topologies derived from SoC designs, thus enabling the use of the LBDRx approach in application-specific SoC systems. J.Cano et al. in [11], [21] has also proposed a tool to map the initial irregular topology into a logical regular structure where the LBDRx approach can be used. "
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    ABSTRACT: The availability of increased number of resources on a single silicon chip is enforcing the designers to come up with mechanisms for efficient and effective management of these resources on a chip. Moreover defective components, chip virtualization and power-aware techniques may lead to irregular on chip interconnection topology making efficient routing a non trivial challenge. Nearly, all routing algorithms and topologies support switches that make use of routing tables for efficient routing. However memories do not scale well in terms of area and power consumption for the routing tables, thus not practical for scalable on chip networks. Logic based distributed routing (LBDR) is recently proposed as an alternative solution to the table based distributed routing which can drastically reduce the memory requirement even while being as efficient as table based distributed routing. LBDR is a simple methodology of routing that enables the removal of the routing tables at every switch and uses only a small set of bits per switch to enable efficient routing. This paper surveys different variations of efficient Logic-based distributed routing (LBDR) proposed in the NoC research literature for regular and irregular on chip interconnection topologies.
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    ABSTRACT: High-end MPSoC systems with built-in high-radix topologies achieve good performance because of the improved connectivity and the reduced network diameter. In high-end MPSoC systems, fault tolerance support is becoming a compulsory feature. In this work, we propose a combined method to address permanent and transient link and router failures in those systems. The LBDRhr mechanism is proposed to tolerate permanent link failures in some popular high-radix topologies. The increased router complexity may lead to more transient router errors than routers using simple XY routing algorithm. We exploit the inherent information redundancy (IIR) in LBDRhr logic to manage transient errors in the network routers. Thorough analyses are provided to discover the appropriate internal nodes and the forbidden signal patterns for transient error detection. Simulation results show that LBDRhr logic can tolerate all of the permanent failure combinations of long-range links and 80% of links failures at short-range links. Case studies show that the error detection method based on the new IIR extraction method reduces the power consumption and the residual error rate by 33% and up to two orders of magnitude, respectively, compared to triple modular redundancy. The impact of network topologies on the efficiency of the detection mechanism has been examined in this work, as well.
    Networks on Chip (NoCS), 2012 Sixth IEEE/ACM International Symposium on; 01/2012