Integrated Design & Test: Conquering the Conflicting Requirements of
Low-Power, Variation-Tolerance, and Test Cost
Ashish Goel, Swaroop Ghosh, Mesut Meterelliyoz, Jeff Parkhurst1 and Kaushik Roy
Purdue University, 1Intel Corporation
465 Northwestern Avenue, West Lafayette, IN-47907, email:email@example.com
Abstract- Design objectives of robustness and low-power usually
do not go hand in hand with the test objectives of maximum test
coverage and minimum test cost. Low power robust design
techniques such as dual-Vth, dual-VDD, or adaptive body biasing
have negative impact on the associated test cost. Similarly, test
techniques like enhanced scan have large overhead in terms of
area and power. In this paper, we try to mitigate the conflicting
design and test requirements using an integrated approach to
design and test that utilizes the existing low power and error
resilient design techniques and augments them to improve test
coverage and cost. Simulation results on an example 8x8 Wallace
tree multiplier in 90nm technology node show 20% reduction in
operating power, 60% reduction in test power and 99%
reduction in critical paths while at the same time improving the
yield from 96% to 100%, compared to existing design and test
methodologies. All this comes at the cost of a marginal increase in
The insatiable demand for higher integration and improved
throughput has led to aggressive scaling of transistor dimensions.
Today, we are at the 45nm technology node while the 22nm node can
be seen on the horizon. However, scaling has not come for free –
leakage current has increased exponentially every generation, the
variations in process parameters have gone up leading to introduction
of new design methodologies, while the cost for verification and test
of integrated circuits have sky-rocketed because of the number of test
vectors and the tester time requirements. Let us consider each of the
above issues in more details to understand the design and test
requirements of future scaled technologies.
In the sub-50nm domain, process imperfections due to sub-
wavelength lithography and intrinsic device level variations have led
to large variations in the transistor parameters. Process parameter
variation is generally classified into two categories: die-to-die (D2D)
variation, which has a strong spatial correlation, and can be thought
to affect each transistor on the die in a systematic way; and within-
die (WID) variation, which is much less spatially correlated. The two
predominant sources of WID variation in small geometry devices are
random dopant fluctuation (RDF) and line-edge roughness (LER) [2,
3]. RDF is mainly due to the distribution of a few tens of dopant
atoms within a small channel. Line-edge roughness is caused due to
sub-wavelength lithography. Both these effects lead to large
variations in transistor parameters like ON current, OFF current,
threshold voltage etc. and pose major design concern. Unfortunately,
the variations not only lead to increased design margining (and
hence, more power consumption), but also leads to new failures in
logic and memories, leading to increased number of test vectors to
target the new failure modes.
Let us consider leakage current in scaled technologies. With
scaling of transistor dimensions, the supply voltage (VDD) has to be
scaled down to maintain the electrostatics of the device and prevent
breakdown caused by high electric fields. Hence, the transistor
threshold voltage (Vth) and gate oxide thickness has to be
commensurately scaled to maintain a high drive current and to
achieve performance improvement. However, the threshold voltage
scaling and scaling of gate oxide thickness results in substantial
increase in subthreshold and gate leakage current. This increase in
leakage power combined with increasing number of transistors leads
to increase in power with every technology generation. To cope with
such increased leakage, several circuit level techniques have been
proposed. Such techniques include Transistor-stacking , input-
vector control , Dual Vth , Dual VDD , Multi-threshold-
voltage CMOS , Dynamic threshold CMOS . In addition to
increase in area, these design techniques may have conflicting
requirements with standard test methodologies. For example, Dual-
Vth designs use high Vth transistors in the non-critical paths, thus
slowing them down. This skews the path distribution and increases
the number of paths with delays close to critical path . Thus, under
process variation all these paths need to be tested to prevent any
delay failures. This increases both the number of test vectors and the
possible delay faults that need to be tested, resulting in increased test
Successful products rely on combination of good design and
effective test and inspection. In the design domain, the main
objectives are power and robustness to process variation. In the test
domain, the aim is to maximize test coverage and minimize test time.
Both design and test objectives sometimes have conflicting
requirements and methodologies. However, we have noted that some
design features that are geared towards low-power or error resilient
designs can also be effectively used for testing circuits to reduce test
cost and enhance on-chip testability. Thus, to provide an optimal
design, we believe that there is a need for integrated design and test
methodology that effectively uses the design methodologies to reduce
both test cost and achieve low power and robustness to process
In this work, we present an integrated test and design
1. Utilizes the existing low power and error resilient design
techniques to reduce operating power while at the same time
reducing the test cost (both stuck at and delay faults).
2. Augments low power design technique with low power test
techniques to decrease the test power with minimal impact on
power and performance of the Circuit Under Test (CUT).
3. Makes use of on-chip process sensors to augment test and to
reduce the external test cost.
The rest of the paper is organized as follows: Section II shows the
motivation behind our work. Section III discusses the various low
power and error resilient design techniques and their impact on test.
Section IV discusses various low power test techniques which are
helpful in increasing the test coverage for delay fault testing. Section
V applies the integrated test and design methodology on an 8x8
Wallace tree multiplier and shows the results and we conclude in
II. PRELIMINARIES & MOTIVATION
Let us look at how the design frequency, power and test requirements
change when we design based on nominal and worst case scenario.
To show the differences, let us consider an example 8x8 Wallace
Tree multiplier (WTM), shown in Fig. 1. It consists of a tree
(consisting of four stages of full adders and half adders) and a
merging adder. The final vector merging adder (VMA) is
implemented as a cascaded carry select adder (CCSA) .
2011 Asian Test Symposium
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Fig. 8 (a) Test Power and (b) Normal mode power (c) Area for conventional and CRISTA multiplier with application of FLH and BIDS
During normal mode of operation BIDS is turned off, thus there is no
increase in operating power consumption. During test mode,
however, we see an increase in power consumption due to addition of
BIDS. This results in reduction of power savings from 81% to 60%.
The area penalty is marginal and the overall increase in area
(CRISTA with FLH and BIDS) is just 7.8%.
Thus, by using CRISTA multiplier along with FLH and BIDS we
can get lower test power (60%), improved test coverage and lower
test cost along with lower operating power (21%) at the cost of
marginal increase in area (7.78%).
In this paper, we have presented an integrated design and test
methodology which utilizes existing design and test techniques to
reduce the operating power and test cost. The proposed methodology
overcomes the conflicting requirements of low power error resilient
design and test by making suitable design choices. We applied the
methodology to an 8x8 Wallace tree multiplier and show a large
reduction in operating and test power along with improvement in test
coverage and cost.
Acknowledgement: The research was funded in part by Semiconductor
Research Corporation and by Gigascale System Research Center (GSRC)
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