Integrated Design & Test: Conquering the Conflicting Requirements of Low-Power, Variation-Tolerance and Test Cost.

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Integrated Design & Test: Conquering the Conflicting Requirements of
Low-Power, Variation-Tolerance, and Test Cost
Ashish Goel, Swaroop Ghosh, Mesut Meterelliyoz, Jeff Parkhurst1 and Kaushik Roy
Purdue University, 1Intel Corporation
465 Northwestern Avenue, West Lafayette, IN-47907, email:goel0@purdue.edu

Abstract- Design objectives of robustness and low-power usually
do not go hand in hand with the test objectives of maximum test
coverage and minimum test cost. Low power robust design
techniques such as dual-Vth, dual-VDD, or adaptive body biasing
have negative impact on the associated test cost. Similarly, test
techniques like enhanced scan have large overhead in terms of
area and power. In this paper, we try to mitigate the conflicting
design and test requirements using an integrated approach to
design and test that utilizes the existing low power and error
resilient design techniques and augments them to improve test
coverage and cost. Simulation results on an example 8x8 Wallace
tree multiplier in 90nm technology node show 20% reduction in
operating power, 60% reduction in test power and 99%
reduction in critical paths while at the same time improving the
yield from 96% to 100%, compared to existing design and test
methodologies. All this comes at the cost of a marginal increase in
area (7.8%).
I. INTRODUCTION
The insatiable demand for higher integration and improved
throughput has led to aggressive scaling of transistor dimensions.
Today, we are at the 45nm technology node while the 22nm node can
be seen on the horizon. However, scaling has not come for free –
leakage current has increased exponentially every generation, the
variations in process parameters have gone up leading to introduction
of new design methodologies, while the cost for verification and test
of integrated circuits have sky-rocketed because of the number of test
vectors and the tester time requirements. Let us consider each of the
above issues in more details to understand the design and test
requirements of future scaled technologies.
In the sub-50nm domain, process imperfections due to sub-
wavelength lithography and intrinsic device level variations have led
to large variations in the transistor parameters. Process parameter
variation is generally classified into two categories: die-to-die (D2D)
variation, which has a strong spatial correlation, and can be thought
to affect each transistor on the die in a systematic way; and within-
die (WID) variation, which is much less spatially correlated. The two
predominant sources of WID variation in small geometry devices are
random dopant fluctuation (RDF) and line-edge roughness (LER) [2,
3]. RDF is mainly due to the distribution of a few tens of dopant
atoms within a small channel. Line-edge roughness is caused due to
sub-wavelength lithography. Both these effects lead to large
variations in transistor parameters like ON current, OFF current,
threshold voltage etc. and pose major design concern. Unfortunately,
the variations not only lead to increased design margining (and
hence, more power consumption), but also leads to new failures in
logic and memories, leading to increased number of test vectors to
target the new failure modes.
Let us consider leakage current in scaled technologies. With
scaling of transistor dimensions, the supply voltage (VDD) has to be
scaled down to maintain the electrostatics of the device and prevent
breakdown caused by high electric fields. Hence, the transistor
threshold voltage (Vth) and gate oxide thickness has to be
commensurately scaled to maintain a high drive current and to
achieve performance improvement. However, the threshold voltage
scaling and scaling of gate oxide thickness results in substantial
increase in subthreshold and gate leakage current. This increase in
leakage power combined with increasing number of transistors leads
to increase in power with every technology generation. To cope with
such increased leakage, several circuit level techniques have been
proposed. Such techniques include Transistor-stacking [1], input-
vector control [2], Dual Vth [3], Dual VDD [4], Multi-threshold-
voltage CMOS [5], Dynamic threshold CMOS [6]. In addition to
increase in area, these design techniques may have conflicting
requirements with standard test methodologies. For example, Dual-
Vth designs use high Vth transistors in the non-critical paths, thus
slowing them down. This skews the path distribution and increases
the number of paths with delays close to critical path [7]. Thus, under
process variation all these paths need to be tested to prevent any
delay failures. This increases both the number of test vectors and the
possible delay faults that need to be tested, resulting in increased test
cost.
Successful products rely on combination of good design and
effective test and inspection. In the design domain, the main
objectives are power and robustness to process variation. In the test
domain, the aim is to maximize test coverage and minimize test time.
Both design and test objectives sometimes have conflicting
requirements and methodologies. However, we have noted that some
design features that are geared towards low-power or error resilient
designs can also be effectively used for testing circuits to reduce test
cost and enhance on-chip testability. Thus, to provide an optimal
design, we believe that there is a need for integrated design and test
methodology that effectively uses the design methodologies to reduce
both test cost and achieve low power and robustness to process
variation.
In this work, we present an integrated test and design
methodology which:
1. Utilizes the existing low power and error resilient design
techniques to reduce operating power while at the same time
reducing the test cost (both stuck at and delay faults).
2. Augments low power design technique with low power test
techniques to decrease the test power with minimal impact on
power and performance of the Circuit Under Test (CUT).
3. Makes use of on-chip process sensors to augment test and to
reduce the external test cost.
The rest of the paper is organized as follows: Section II shows the
motivation behind our work. Section III discusses the various low
power and error resilient design techniques and their impact on test.
Section IV discusses various low power test techniques which are
helpful in increasing the test coverage for delay fault testing. Section
V applies the integrated test and design methodology on an 8x8
Wallace tree multiplier and shows the results and we conclude in
section VI.
II. PRELIMINARIES & MOTIVATION
Let us look at how the design frequency, power and test requirements
change when we design based on nominal and worst case scenario.
To show the differences, let us consider an example 8x8 Wallace
Tree multiplier (WTM), shown in Fig. 1. It consists of a tree
(consisting of four stages of full adders and half adders) and a
merging adder. The final vector merging adder (VMA) is
implemented as a cascaded carry select adder (CCSA) [8].
2011 Asian Test Symposium
1081-7735/11 $26.00 © 2011 IEEE
DOI 10.1109/ATS.2011.100
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Considering nominal process corner, the WTM shows a critical path
delay of 2.16ns with a power consumption of 433nW and area of
1521um2. However, under the affect of process variation, two things
can happen: (1) the critical path delay can increase considerably (2) a
lot of non-critical paths which had delays close to the critical path
can now become critical. To achieve the target yield target, a worst
case corner design approach can be adapted. In this approach, the
transistors have to be properly up-sized to meet the delay requirement
even under extreme process variation. For the 8x8 WTM, when we
do a worst case corner design, the power consumption increases to
542nW and the area increases to 1830um2. This increase in power
(both static and dynamic) and area occurs because the gates are sized
up to meet the delay requirements at the slow D2D threshold voltage
corner. However, because of the sized up gates, the delay of the
circuit reduces at the nominal corner. This can lead to a reduction in
the associated test cost. From both design and test objectives, we
would like to get the test benefits of designing at worst case corner
without paying the cost of additional power and area. Thus, we need
to investigate techniques which can result in improved yield without
increasing power and area while achieving reduction in test cost.
III. LOW POWER AND ERROR RESILIENT DESIGN
TECHNIQUES
Various techniques have been proposed for low power and process
variation tolerant designs. Some of these techniques are post-Si like
Adaptive Body Biasing (ABB) [9], RAZOR [10], while, some others
are design time techniques
Trifecta/CRISTA [11,16], Dynamic Supply Gating [12] and Dual
Length-Dual Vth . Let us look at some of these techniques in further
detail and their impact on test cost.
Leakage power is a major component of power in scaled
technologies. As mentioned above, Dual Vth assignment has been
used as a static method for reducing the leakage power. However,
dual Vth technique does not reduce the leakage in critical paths.
Moreover, dual Vth assignment increases the number of critical paths
in a design, degrading the design yield under process variations [13].
Leakage and performance are dependent on Vth of the devices.
Performance can be improved by lowering Vth of the devices,
however, that leads to higher leakage current. One possible way to
tradeoff leakage and performance is to apply a separate bias to
critical devices. Device Vth can be modulated for lower leakage by
applying reverse body bias (RBB), and, applying forward body bias
(FBB), for higher performance. It is possible to utilize both of these
approaches and perform trade-off between leakage and performance
by using Adaptive Body Bias (ABB). FBB is applied to the chips in
the slow process corner to increase the performance and RBB is
like Dual Vth, Dual-VDD,
applied to the chips in the fast process corner (hence, high leakage) to
reduce the leakage. This application of RBB and FBB results in more
chips meeting the leakage and performance requirement and leads to
an increase in yield. However, proper application of ABB requires
additional bias circuitry and additional power grids. In addition, the
dies need to be binned according to the amount of body bias that
needs to be applied to each individual chips. These factors raise the
need for additional test vectors and/or change in testing methodology
to properly verify these circuits, thus, giving rise to test cost.
Supply gating has been proposed as a method to reduce standby
leakage current [14]. Sleep transistors are connected in series either
to VDD or GND to shut down power to the idle parts of the circuit and
save leakage power. However, supply-gating is geared towards stand-
by power reduction. [12] provides an effective method to reduce
active power (both leakage and switching) using supply gating. The
authors propose a new synthesis methodology based on Shannon
expansion [15]. Shannon expansion partitions any Boolean
expression into disjoint sub-expressions based on a control variable
(xi).
( ,.., ,..,). ( ,..,1,..,
inii
f xxx x f xx
??
..
ii
x CF
??

where CF1 =
1
( ,..,1,..,)
in
f xxx
?
are called cofactors. Depending on the state of the control variable xi,
only one of the cofactors (CF1 or CF2) provides the output. The
output of CF1 and CF2 are combined using a multiplexer (MUX)
close to the primary output, which is controlled by xi (Fig. 2). Thus,
if the supply gating transistors of CF1 and CF2 are controlled by xi
and
sub-expression, resulting in reduced leakage and switching power.
The methodology can be extended hierarchically for multi-level
expansion to further improve power savings. [22] studied the effect
of Shannon based synthesis on test cost. The authors show that the
synthesis style can improve the testability (test time and coverage) of
a circuit significantly and also reduce test cost. This occurs because
of the increased observability of the internal nodes (due to isolation
of control variables and addition to the select line of the MUX close
to the primary output). Thus, Shannon based supply gating is not
only suitable for designing low power circuit, but it also helps in
reducing the associated test cost.

Another application of Shannon based synthesis is CRISTA [16].
CRISTA achieves robustness to process variation and provides
opportunity for voltage over-scaling by confining the long paths of
the synthesized circuit to known logic blocks, thus, achieving critical
path isolation. Here, long paths are defined so as to include critical
paths and the paths which have delays close to the delay of critical
paths. Thus, long paths are essentially those paths which can become
critical under process variation. Similarly, short paths are defined as
the paths which will not become critical even under extreme process
variation. The long paths are predictable and rare by design so that
under reduced supply voltage, possible delay errors under single
111
) . ( ,..,
x f x
0,..,)
niin
xxx
??


12
x CF
and CF2 =
1
( ,..,
f x
0,..,)
in
xx
?

ix , it provides an opportunity for gating the supply of the idle

Fig. 2 Shannon Expansion (a) basic idea (b) after supply gating

Fig. 1 An 8x8 Wallace tree multiplier depicting the critical path
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Fig. 4 CRISTA design methodology
cycle operation are deterministic, and can be avoided by two-cycle
operation (assuming all operations are single-cycle).
Isolation of long paths is easy if we consider cases where there
are very few long paths (for example ripple carry adder). However, a
random logic can have many long paths and corresponding input
conditions to predetermine their activation. Furthermore, the critical
paths among these long paths can vary from chip to chip due to
process variation. Thus to make sure that supply voltage can be
scaled, the following conditions need to be met: (1) the long paths
(including the critical paths) are to confined to a predictable logic
section and (2) the short paths remain off-critical even under process
variation by providing a safe amount of timing slack. This timing
slack will enable us to lower the supply voltage of the circuit. An
example of a possible path delay distribution is shown in Fig. 3. It
illustrates how long paths are isolated from shorter paths using a
timing slack. Furthermore, it shows that the long paths may have
delays larger than the delay target determined by the operating
frequency (as shown by the solid bar in Fig. 3). However, if the long
path activation probability is low and predictable, then we can avoid
the delay failures by allowing an extra cycle for the completion of the
operation.
To obtain the delay distribution shown in Fig. 3, the design needs
to be partitioned and synthesized in such a way that the paths are
divided into several logic blocks. The partitioning procedure should
consider the following: 1) these logic blocks can be active or remain
idle based on the state of primary inputs and 2) the probabilities of
activation of the logic blocks containing long/critical paths (called
critical block) are very low. Therefore, it is possible to predict the
activation of a logic block (and the corresponding paths) just by
decoding the states of inputs. To achieve the two objectives, CRISTA
utilizes Shannon expansion based synthesis. First, the circuit is
partitioned, and the cofactors containing the critical paths are
determined. These cofactors are then further expanded hierarchically
(as explained above) to reduce the activation probability of the
long/critical paths. Next, gate sizing can be performed on the
partitioned logic blocks to maximize the slack between long/critical
and noncritical blocks (containing the short paths) leading to further
isolation of critical paths. By performing the partitioning and sizing,
a path delay distribution similar to the one shown in Fig. 3 can be
achieved. Finally, supply voltage over-scaling can be done such that
noncritical blocks meet the desired timing yield with respect to one-
cycle delay target, whereas critical block meet the yield with respect
to two-cycle delay target. The overall design flow is shown in Fig. 4.
Let us discuss the test implications of applying CRISTA. As
mentioned above, we isolate the long paths and create slack between
the long and short paths by gate sizing. The sizing is done so as to
make sure that the isolated long paths meet 100% yield target under
two-cycle delay target, even under scaled supply voltages. This
obviates the need to test the long paths for delay faults. The short
paths, on the other hand, are designed to meet the yield target under
single-clock-cycle delay. These short paths are now the critical paths
of the design under scaled voltage operation. Therefore, delay testing
has to be done only for short paths at lower supply voltage. This is
contradictory to conventional delay testing strategy where testing is
performed on long paths. These factors combined with the increased
observability of internal nodes and/or reduced area (as explained
above) results in large reduction in the associated test cost. Thus,
CRISTA design methodology can be used to design process resilient
low power circuit while at the same time increase the test coverage
and reduce the associated test cost (also, note that voltage scaling and
error resiliency are two sides of the same coin).
IV. TEST TECHNIQUES
In the previous section, we looked at various design techniques and
their implications on test cost in terms of test time, number of test
vectors and test power. We observed that some techniques (Dual
VDD, Body biasing etc.), though useful in designing robust and low
power circuits are detrimental to the purpose of reducing test cost and
increasing test coverage. However, there are other techniques based
on Shannon based expansion (Supply gating, CRISTA) which not
only helps in designing low power robust circuits, but also reduces
the associated test cost and/or improves test coverage. The next step
now is to look at test techniques which have minimal impact on the


Fig. 3 Path delay distribution required for CRISTA

Fig. 5 First Level Hold (FLH) depicting the gating at first level gates. Inset shows the gating circuit in detail
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power and performance of the CUT. These techniques can then be
effectively applied along with the above discussed design techniques
to reduce power during both test mode and normal mode of
operations and/or improve the test cost.
Delay faults are usually tested using enhanced scan testing,
which is particularly useful for path delay fault testing, where a set of
critical timing paths need to be sensitized and tested for delay
violations. Although enhanced scan has high combinational path
testability, it involves high DFT overhead due to addition of extra
hold latch at the output of each scan flip-flop. This extra latch also
affects the performance of the CUT during normal mode of operation
as it lies in the stimulus path between the scan flip-flops and the
combinational logic. In addition to affecting performance, the latch
also takes up significant amount of die-are and consumes power in
normal mode. Thus, this technique is detrimental to the design of low
power circuits.
First Level Hold (FLH) [17] is a technique which has been
proposed to perform two pattern delay testing similar to enhanced
scan. This technique applies the principle of supply gating to hold the
state of the combinational logic. Thus, instead of holding the pattern
in the hold latch as is done in enhanced scan, FLH holds the state of
the combinational circuit by gating the VDD and GND of the first
level gates. Fig. 5 shows the scan architecture with hold logic at the
first stage. As can be seen, FLH uses two gating transistors, one in
the pull-up and other in the pull-down to gate the supply lines for the
first level logic gates during the scan shifting. Hence, the output state
of the first level logic gates at the fanout cone of the scan flip-flops
hold their state, irrespective of the activity in the scan registers due to
rippling of scan values. Once the first level logic gates hold their
states, the other levels also retain their states, since no signal activity
propagates to them. Thus, FLH can reduce the test power
considerably over enhanced scan because it prevents redundant
switching in the combinational logic during scan shifting and reduces
the leakage power as well due to stacking of transistors. Moreover,
during normal mode of operation the series connected gating
transistors also help in reducing the active leakage of the circuit due
to “stacking” effect. Thus FLH can be an effective technique to
reduce test power without impacting (or in some cases improving)
the power and performance of CUT during normal mode of
operation.
Along with reducing test power, improving test coverage is a
major objective for any test scheme. Test Point Insertion (TPI) is a
very effective solution for improving the controllability and
observability of internal nodes of a circuit [18]. TPI can be helpful in
improving the test coverage of a circuit. TPI for stuck-at-faults in
scan-based BIST has been explored extensively. However, very little
work has been done on delay fault coverage improvement using TPI.
The main reason is the unavailability of a delay sensing hardware
that can act as an observation point for the intermediate nodes. [19]
reports a process tolerant delay sensor which can be inserted at
strategic nodes to increase the fault coverage or reduce the test

application time. Fig. 6 shows the delay sensing scheme and the
timing diagram of the circuit. The circuit works on the principle of
converting delay to a voltage level and then comparing it to a
reference voltage level to determine whether the delay is more than a
reference delay or not. Let us assume node X makes a falling
transition from “1” to “0” and TD is the time interval between the
rising clock edge and the time when the voltage the node X makes
falling transition. Let TMAX be the maximum delay that can be
tolerated so that TD>TMAX would mean a delay failure. The sawtooth
generator is so designed to have the pulse duration T equal to the
clock (this is done by generating the waveform from the reference
clock). The output of the sawtooth generator is fed into a track-and-
hold (TAH) circuit, and the sampling switch is controlled by the node
X. Thus as long as node X stays high, TAH switch in ON and the
output of TAH tracks the sawtooth waveform. When X makes a
falling transition, it turns OFF the TAH switch, and the output
capacitor of TAH holds the value (say VHOLD). This value is fed into
a comparator which compares VHOLD with a reference voltage VREF
(which is a measure of the maximum tolerable delay TMAX) when
comparator enable (CE) goes high at the next clock cycle. Thus,
whenever VHOLD < VREF we have a delay failure and the comparator
output gives a “0”. The details about the implementation of the
sensor are given in [19].
Fig. 7 shows a scheme which can detect delay in both rising and
falling transition. It connects BIDSr and BIDSf in parallel which
receive the original (S) and the complemented (~S ) signals from the
net under consideration. The decision for a rising transition is made
by BIDSr and by BIDSf for a falling transition. When the delay meets
the criteria, the output of the BIDS is a “1”. Thus, if we XOR the
outputs of BIDSr and BIDSf, a delay fault is detected if the output of
XOR is “0”.
One important point to note is that the output of the sensor does
not require any response analyzer for a pass-fail decision. Instead, the
pass-fail decision is automatically available at the XOR output.
Moreover, insertion of BIDS has minimal area and delay overhead.
The sawtooth generator and reference voltage generator blocks can
be shared by all BIDS blocks. [19] reports that delay overhead due to
BIDS insertion is less than 1% in the critical paths of ISCAS89
benchmarks while giving close 10% improvement in test coverage on
average. The number of test points required to achieve this
improvement was less than 10, thus making the scheme attractive for
improving the test coverage with minimal power (both test and
normal mode), area and delay overhead.
In this section we have seen two techniques (FLH and Built-In
Delay Sensor) which can be used to reduce the power overhead and
improve the test coverage respectively in circuits. Both the
techniques have minimal impact on the normal operation on CUT,
thus making them compatible to be used with low power process
resilient design techniques. In the next section we will discuss how
these test techniques can be effectively integrated with the previously
discussed design techniques to achieve a low power error resilient

Fig. 6 Built-in-Delay Sensor (BIDS) (a) Delay sensing scheme (b) Timing
diagram of the circuit

Fig. 7 Schematic for sensing rising and falling transition delays using BIDS
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design with improved test coverage at a reduced test cost.
V: INTEGRATED APPROACH: WALLACE TREE
MULTIPLIER
In the previous sections we have discussed various low power and
variation tolerant design techniques which are amenable to reduced
test cost. We also discussed test techniques which improve test
coverage while having minimal impact on the power and
performance of CUT. However, to develop an optimal system we
need to integrate the design and test techniques together. In this
section, we show an integrated approach to utilize the above
mentioned techniques and apply them to an 8x8 Wallace Tree
multiplier to obtain a low power design with reduced test cost and
improved test coverage.
Fig. 1 shows an 8x8 Wallace tree multiplier (WTM) with a tree
(consisting of four stages of full adders and half adders) and a
merging adder. As mentioned in section II, the final vector merging
adder (VMA) is implemented as a cascaded carry select adder
(CCSA). The first step in the process would be to apply CRISTA
design methodology on the multiplier. To apply CRISTA we need to
isolate the critical paths so that the activation of the critical can be
predicted based on the inputs by using a decoder. However, as can be
seen from fig. 1, WTM has many paths with similar delays and under
process variation any one of these paths may become critical. Hence,
we make an assumption that all potential critical paths, in presence of
variability, have the carry propagation path of the VMA in common.
The critical path delay in a WTM is equal to the sum of the path
delays through the tree stage (each stage contributes an adder delay)
and the delay through the VMA. Thus, for the 8x8 WTM the critical
path delay is the sum of four adder delays and the worst case
propagation delay of VMA. We apply the CRISTA methodology on
the VMA adder and use the VMA inputs (rather than the multiplier
inputs) as the inputs to the decoder. We also note that there is a great
potential to be exploited in case of WTM because of the relatively
large size of the VMA. This can give us opportunity for aggressive
voltage over-scaling, resulting in large power savings.
Table I shows the power savings and the area overhead of the
CRISTA based multiplier design. We used Verilog to design the
multiplier. The Verilog code was synthesized using Synopsis Design
Compiler [20] and 90nm technology library. In order to obtain the
parametric yield in presence of process variations, we ran Monte
Carlo simulations in Hspice, assuming a Gaussian Vth variation
distribution of zero mean and standard deviation of 40 mV. The
power dissipation results were obtained by simulating 500 random
input vectors in Hspice. As we can see, we can lower down the
supply voltage of the CRISTA multiplier down to 0.9V while still
meeting the yield target of 96%. This results in power saving of
about 21% at the cost of 6.6% area overhead. It is important to note
that if we operate CRISTA multiplier at nominal VDD (VDD=1V) we
can get 100% yield, however, we have to operate the conventional
multiplier at 1.1V to get 100% yield and can get a maximum of 96%
yield at VDD=1V. The amount of power savings can increase if we
increase the number of bits in the multiplier. This is because as we
increase the number of bits, the size of VMA increases and gives us
more opportunity for voltage over-scaling.
Once, we have applied CRISTA on the multiplier to reduce the
power consumption, we need to introduce the test techniques. For
this, we first implement FLH on the first level gates. To improve the
coverage, we need to insert delay sensors at hard-to-observe nodes.
This can be done using the methodology given in [19]. Table II and
Fig. 8 show the results of introducing FLH and the BIDS in the
conventional and CRISTA multiplier. We have used Tetramax [21]
to get the test vectors and the test coverage. As we can observe,
adding FLH reduces the test power by 77% with a negligible increase
in area. Using CRISTA along with FLH results in 21% reduction in
operating power and 81% percent reduction in test power. The
operating power reduction is obtained because we can operate the
CRISTA multiplier at lower power supply (VDD=0.9V) while still
achieving the yield target. There is a marginal area penalty (7.2%).
This mainly comes from the pre-decoder used to detect the two-cycle
operations. We can achieve very high fault coverage (Transition and
Stuck-At faults) for the conventional multiplier using 200 patters.
However, as mentioned in section II, when we use CRISTA we can
reduce the number of patterns required to 164 (Table II).

The most important part where we see the impact of using
CRISTA methodology is in the reduction of the number of critical
paths. The number of critical paths can be directly related to the
amount of test vectors we need to test the circuit. We see a 89.6%
reduction in the number of critical paths (Fig. 9: 2259 to 235). Let us
understand why this happens: The maximum delay in the circuit
(under no process variation) is from input A[1] to output P[15]. Let
us call this delay TNOM. Under process variation and scaled supply
voltage, a lot of paths with delays close to TNOM can become critical.
Thus, to ensure that there are no delay faults we need to test paths
that have delays close to the critical path for delay faults. Let us
assume that we check for the paths that have delays greater than
TTHRES (=0.8*TNOM). It is assumed here that none of the paths with
delays less than TTHRES will become critical under process variation
and scaled supply voltage. Then the number of paths having delays
greater than TTHRES is 2259. These are the paths ending at P[15]-P[9].
The distribution of these paths is shown in Fig. 9. For the
conventional multiplier, we will have to test all these paths as any of
these paths can become critical under process variation. However,
when we use the proposed CRISTA based multiplier, the paths
ending at P[15]-P[11] are the long paths. We may not need to carry
out delay fault testing for these paths as we will perform two-cycle
operation whenever these paths are activated based on the inputs to
the pre-decoder (note that such paths do have enough timing slack for
2-cycle operation). The critical paths in the CRISTA based multiplier
will be from the short paths. These are the paths ending at P[10] and
P[9] (with a delay more than TTHRES). The paths have to meet the
single cycle delay target under reduced power supply and can
become critical under process variation. Thus, we now need to check
these paths for delay failures.
Adding BIDS on top of FLH helps in increasing the test coverage
for transition faults. We have used BIDS at five hard-to-detect nodes
for both the conventional and CRISTA multiplier. The five BIDS
share the sawtooth generator and the voltage reference generator.
Table II. Comparison of Conventional and CRISTA multiplier with application of FLH and BIDS
Conventional (with Hold
Latch for delay testing)
No. of
Faults Patterns Coverage Faults Patterns Coverage
4756 200 99.79 4756 200 99.79
Conventional with FLH CRISTA with FLH (6-bit
decoding)
No. of
FaultsPatterns
4320 164
Conventional with FLH and
Sensors
No. of
FaultsPatterns
4762 205
CRISTA with FLH and
Sensors
No. of
FaultsPatterns
4320 178
No. of % No. of No. of % No. of %
Coverage
99.79
No. of %
Coverage
99.91
No. of %
Coverage
99.91
Transition
Patterns
Stuck-At
Patterns
No. of Critical
Paths
4756 200 99.79 4756 200 99.79 4320 164 99.79 4762 205 99.79 4320 178 99.79
2259 2259 235(-89.6%) 2259 235(-89.6%)
Table I. Yield, Power and Area comparison for Conventional and
CRISTA multiplier with 6-bit decoding
Operating
Voltage for
96% Yield
Conventional 1.0
CRISTA 0.9 252.6(-21%)
Power (uW)
Area
Overhead
-
6.6%
Operating
Voltage for
100% Yield
1.1V
1.0V
307.21
490