Conference Paper

A hybrid memory organization to enhance task migration and dynamic task allocation in NoC-based MPSoCs

DOI: 10.1145/1284480.1284557 Conference: Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2007, Copacabana, Rio de Janeiro, Brazil, September 3-6, 2007
Source: DBLP


Regarding MPSoCs, dynamic task allocation and task migration are still open research areas and, for both of them, there is no clear memory organization winner. While bus-connected systems commonly use a shared memory paradigm, NoC-based ones easily allow the exploration of distributed memory alternatives. This paper proposes a hybrid memory organization for NoC-based systems as the way to minimize the energy spent during the code transfer when task migration or dynamic task allocation needs to be performed. In our hybrid approach, the code can be transferred from the node where the task was originally running or from a memory positioned at the center of the system. The choice between the two options is done at runtime in a very intuitive way, based on the distance between the nodes involved on the transfer. Results are very encouraging and indicate that the proposed hybrid organization reduces the code transfer energy by 24% and 10% on average, as compared to global- and distributed-only memory organizations, respectively.

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Available from: Eduardo Wenzel Brião, Mar 25, 2014
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    • "Barcelos et al. [9] proposed a hybrid memory organization approach which supports the task migration algorithms with low-energy consumption constraints. In this approach, the data to be migrated can be provided either by the source node or from the shared memory. "
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    ABSTRACT: In deep submicron circuits, high temperatures have created critical issues in reliability, timing, performance, coolings costs and leakage power. Task migration techniques have been proposed to manage efficiently the thermal distribution in multi-processor systems but at the cost of important performance penalties. While traditional techniques have focused on reducing the average temperature of the chip, they have not considered the effect that temperature gradients have in system reliability. In this work, we explore the benefits of thermal-aware task migration techniques for embedded multi-processor systems. We show the implementation issues of task migration policies on next generation architectural template of distributed memory multicore systems and we discuss the programmer’s implications. Built on top of this programming model, we propose several policies that are able to reduce the average temperature of the chip and the thermal gradients with a negligible performance overhead. With our techniques, hot spots and temperature gradients are decreased up to 30% with respect to state-of-the-art thermal management approaches.
    12/2010: pages 83-115;
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    • "Task migration is very popular and is widely used in the distributed systems field. On the other hand, it is a relatively new research area in the field of real-time embedded systems [19] [20] [21]. A test-bed for reconfiguration-based fault-tolerance must have the ability to provide resource reallocation and run-time dynamic task binding to hardware and software components. "
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    ABSTRACT: The continuing employment of distributed embedded systems in various safety critical applications requires the demonstration of a high degrees of dependability. Fault-tolerance is the primary means to achieve dependability at runtime and has been an active research area for decades. In addition to traditional hardware and software redundancy, hybrid and reconfiguration-based approaches to fault-tolerance are evolving. Software simulation techniques are a common starting point for evaluating reconfigurable computing approaches. Simulations, however, typically make an amount of unrealistic assumptions. In this paper, we present a test-bed for the testing and evaluation of reconfiguration-based fault-tolerance approaches. The test-bed uses 16-bit microcontrollers as processing elements. A real-time operating system is used for task scheduling and inter-task communication. The test-beds’ processing elements communicate through a CAN network. Monitoring, user interface, environmental interaction, and fault-injection abilities are provided through a graphical user interface.
    The International Conference on Information and Communications Systems (ICICS2009), Amman, Jordan; 12/2009
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    ABSTRACT: With the development of the semiconductor technology, more processors can be integrated onto a single chip. Network-on-Chip is an efficient communication solution for many-core system. However, enhancing performance with lower energy consumption is still a challenge. One critical issue is mapping applications to NoC. This work proposed an online mapping method, which optimizes task mapping algorithm to reduce communication energy consumption. The communication status of applications at runtime is analyzed first. Then, the algorithm computes the mapping placement dynamically and implements the real-time mapping online. Experimental results based on simulation show that the algorithm proposed in this article can achieve more than 20% communication energy saving compared with first fit mapping and nearest neighbor mapping. The migration cost caused by the remapping process is also considered, and can be calculated at the runtime to estimate the effect of remapping.
    The Journal of Supercomputing 06/2013; 64(3). DOI:10.1007/s11227-011-0678-1 · 0.86 Impact Factor
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