Generating power-hungry test programs for power-aware validation of pipelined processors.
ABSTRACT As CMOS technology scaled to nanometer regimes (100nm and below) power dissipation and power density have become major design constraints. The power consumed by active devices is converted into heat, which in turn increases the substrate temperature. Working at high temperatures may affect several figures of merit (e.g., frequency and leakage power), as well as the reliability of the entire system. Therefore, considering power consumption during test and design validation procedures has become a testing due for modern SoCs. While a huge range of techniques focus on low-power test, we consider the other side of the problem: how to maximize the power absorbed by a processor core (while still remaining into legal operations) in order to test the robustness, and/or validate the functionality of the surrounding components, and the core itself, under high power operating conditions. In this paper, we first demonstrate the actual difficulty of assembling power-hungry test programs on pipelined processors. Second, we propose an automated methodology, based on an automatic optimizer, that allows a push-bottom generation of high-power consuming programs under user-defined constraints. The proposed flow is validated using an open-source pipelined processor mapped into an industrial 65nm technology
Conference Proceeding: A data dependent approach to instruction level power estimation[show abstract] [hide abstract]
ABSTRACT: The increasing diffusion of portable systems, like mobile computers and phones, or embedded computing applications has driven the need for power analysis and optimization in digital processors used in these systems. In modern CPUs, power estimation and optimization are “two strongly pattern dependent” problems. This means that the influence of the software in power consumption is very high and a power figure for whatever processor must be related to the running software program. Based on the recent techniques already described in literature, we propose a new instruction level power analysis approach, that tries to relate the power dissipation to the executed instructions and their operand valuesLow-Power Design, 1999. Proceedings. IEEE Alessandro Volta Memorial Workshop on; 04/1999
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ABSTRACT: In this paper, we presen t the design and use of a comprehensiv e framework, SimplePower, for ev aluating the e#ect of high-level algorithmic, architectural, and compilation tradeo #s on energy. An execution-driven, cycle-accurate RT lev el energy estimation tool that uses transition sensitive energy models forms the cornerstone of this framework. SimplePower also pro vides the energy consumed in the memory system and on-chip buses using analytical energy models.06/2000;
Conference Proceeding: Evaluation of architecture-level power estimation for CMOS RISC processors[show abstract] [hide abstract]
ABSTRACT: An evaluation of the architecture-level power estimation simulator, ESP (Early design Stage Power and performance simulator), is presented. With ESP, it is possible to accomplish more efficient design by using the architecture-level and gate-level simulator correctly. The estimation and the actual measured results are very similar. In addition, the accuracy of ESP has been improved by 18.3%Low Power Electronics, 1995., IEEE Symposium on; 11/1995