Conference Paper

Generating power-hungry test programs for power-aware validation of pipelined processors

DOI: 10.1145/1854153.1854171 Conference: Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2010, São Paulo, Brazil, September 6-9, 2010
Source: DBLP


As CMOS technology scaled to nanometer regimes (100nm and below) power dissipation and power density have become major design constraints. The power consumed by active devices is converted into heat, which in turn increases the substrate temperature. Working at high temperatures may affect several figures of merit (e.g., frequency and leakage power), as well as the reliability of the entire system. Therefore, considering power consumption during test and design validation procedures has become a testing due for modern SoCs. While a huge range of techniques focus on low-power test, we consider the other side of the problem: how to maximize the power absorbed by a processor core (while still remaining into legal operations) in order to test the robustness, and/or validate the functionality of the surrounding components, and the core itself, under high power operating conditions. In this paper, we first demonstrate the actual difficulty of assembling power-hungry test programs on pipelined processors. Second, we propose an automated methodology, based on an automatic optimizer, that allows a push-bottom generation of high-power consuming programs under user-defined constraints. The proposed flow is validated using an open-source pipelined processor mapped into an industrial 65nm technology

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