Conference Paper

Generating power-hungry test programs for power-aware validation of pipelined processors.

DOI: 10.1145/1854153.1854171 Conference: Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2010, São Paulo, Brazil, September 6-9, 2010
Source: DBLP

ABSTRACT As CMOS technology scaled to nanometer regimes (100nm and below) power dissipation and power density have become major design constraints. The power consumed by active devices is converted into heat, which in turn increases the substrate temperature. Working at high temperatures may affect several figures of merit (e.g., frequency and leakage power), as well as the reliability of the entire system. Therefore, considering power consumption during test and design validation procedures has become a testing due for modern SoCs. While a huge range of techniques focus on low-power test, we consider the other side of the problem: how to maximize the power absorbed by a processor core (while still remaining into legal operations) in order to test the robustness, and/or validate the functionality of the surrounding components, and the core itself, under high power operating conditions. In this paper, we first demonstrate the actual difficulty of assembling power-hungry test programs on pipelined processors. Second, we propose an automated methodology, based on an automatic optimizer, that allows a push-bottom generation of high-power consuming programs under user-defined constraints. The proposed flow is validated using an open-source pipelined processor mapped into an industrial 65nm technology

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    ABSTRACT: High power consumption during test may lead to yield loss and premature aging. In particular, excessive peak power during at-speed delay fault testing represents an important issue. In the literature, several techniques have been proposed to reduce peak power consumption during at-speed LOC or LOS delay testing. On the other hand, some experiments have proved that too much test power reduction might lead to test escape and reliability problems. So, in order to avoid any yield loss and test escape due to power issues during test, test power has to map the power consumed during functional mode. In literature, some techniques have been proposed to apply test vectors that mimic functional operation from the switching activity point of view. The process consists of shifting-in a test vector (at low speed) and then applying several successive at-speed clock cycles before capturing the test response. In this paper, we propose a novel flow to determine the functional power to be used as test power (upper and lower) limits during at-speed delay testing. This flow is also used for comparison purpose between the above-mentioned test scheme and power consumption during the functional operation mode of a given circuit. The proposed methodology has been validated on an Intel MC8051 micro controller synthesized in a 65 nm industrial technology.
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