Conference Proceeding

Low power integrated scan-retention mechanism.

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA;
01/2002; In proceeding of: Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002, Monterey, California, USA, August 12-14, 2002
Source: DBLP

ABSTRACT This paper presents a methodology for unifying the scan mechanism and data retention in latches which leads to scannable latches with the data retention capability achieved at a very low power overhead during the active mode. A detailed analysis of power and area overhead is presented, with layout examples for various common latch styles. Implications of using different power gating techniques for reducing leakage during sleep mode on the design of retention latches are considered, including well biasing for leakage control and sharing wells between gated logic and retention latch devices.

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