Page 1

A Low-Power Design Methodology for High-Resolution

Pipelined Analog-to-Digital Converters

Reza Lotfi Mohammad Taherzadeh-Sani M.Yaser Azizi Omid Shoaei

IC-Design Lab., ECE Dept., University of Tehran,

North Kargar Ave., Tehran, I.R.Iran

E-mail: r.lotfi@ece.ut.ac.ir

ABSTRACT

In this paper a general method to design a pipelined ADC with

minimum power consumption is presented. By expressing the

total static power consumption and the total input-referred noise

of the converter as functions of the capacitor values and the

resolutions of the converter stages, a simple optimization

algorithm is employed to calculate the optimum values of these

parameters, which lead to minimum power consumption while a

specified noise requirement is satisfied. To determine the bias

current values of operational amplifiers, a novel optimal choice

for settling and slewing time parameters is proposed applicable to

both single-stage and two-stage Miller-compensated opamp

structures. Using the proposed methodology, the optimum values

for capacitors, the resolutions and the opamp device sizes of all

stages are determined in order to minimize the total power

consumption. Design examples are presented and compared with

conventional approaches to show the effectiveness of the

proposed methodology.

Categories and Subject Descriptors

B.7.1 [Integrated circuits] Types and Design Styles VLSI (very

large scale integration)

General Terms

Design

Keywords

Low-Power Design, Pipelined Analog-to-Digital Converters,

Operational Amplifiers

1. INTRODUCTION

Pipelining is one of the best approaches to implement high-speed

low-power analog-to-digital converters. Design approaches to

reduce the power consumption of pipelined ADCs are therefore of

great importance to realize medium-to-high resolution high-speed

A/D converters with the least possible power consumption.

Several approaches have been proposed in literature for

systematic design of pipelined A/D converters. In [1] it has been

concluded that to minimize the power consumption of a pipelined

S/Hm1 bitsm2 bitsm3 bits2 bits

DIGITAL ERROR CORRECTION

2

N bits

ANALOG

INPUT

s0

scaling factor:

s1

s2

s3

m1+1

m2+1m3+1

Figure 1. The pipeline ADC structure

ADC, the resolution of all the stages can be chosen equal to 1.5

just in converters with resolutions of less than 10 bits. In [2] a

systematic design methodology has been proposed where

resolutions higher than 1.5 have been proposed for the front-end

stages of the high-resolution converters but the capacitor values of

the stages are not optimized and a predefined noise distribution is

assumed. In [3] the effects of the capacitor scaling, parallelism,

and non-identical resolutions per stages on the pipelined ADC

power consumption are investigated separately. In the latest

reported automatic design tool for pipelined ADCs [4] the

converter is optimized to minimize the power consumption and

area using geometric programming. However, the latter algorithm

is applied to a converter with identical resolution per stages. As

far as we understood it appears that neither of the proposed

approaches are as general yet simple as the approach proposed in

our work.

In this paper with no specific constraint, arbitrary capacitor

scaling as well as non-identical resolution per each stage is

utilized in the design of the converter as shown in Fig. 1.

Effective equations are presented to optimally determine the

capacitor value and the resolution of each stage, in order to

minimize the power consumption of the converter, which makes

use of operational trans-conductance amplifiers (OTAs) with

optimized settling and slewing times.

First, a closed-form equation for the bias current value of a single-

stage or two-stage Miller-compensated opamp is derived

employing an innovative dynamic allocation of the small- and

large-signal settling time parameters. Then the total static power

dissipation of the pipelined ADC is calculated. In section 3, the

total input-referred noise of the converter is derived. Then a

design methodology is presented to minimize the power

consumption with a defined signal-to-noise ratio (SNR). The

input parameters of the optimization CAD tool and related

considerations are addressed. Finally optimization examples

confirming the efficiency of the proposed methodology are

presented and the dependency of the power consumption on the

specifications of the converter is investigated.

Permission to make digital or hard copies of all or part of this work for

personal or classroom use is granted without fee provided that copies

are not made or distributed for profit or commercial advantage and that

copies bear this notice and the full citation on the first page. To copy

otherwise, or republish, to post on servers or to redistribute to lists,

requires prior specific permission and/or a fee.

ISLPED ’03, August 25-27, 2003, Seoul, Korea.

Copyright 2003 ACM 1-58113-682-X/03/0008…$5.00.

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2. OPTIMUM CURRENT OF THE OTA’S

2.1 Optimized bias current of a single OTA

In a switched-capacitor circuit, the outputs of the operational

transconductance amplifiers have to settle to within a very small

fraction of their final values (ess), depending on the required

accuracy of the OTA, in a definite interval called the settling time.

The total settling time including the small-signal (tss) and the

large-signal (tls) settling times should be less than half of the clock

period, i.e.

clklssss

Tttt

=+=

where tother is the rest of the half-period for non-overlapping of

two clock pulses. While tls is due to the limited op-amp slew rate,

tss depends on the finite op-amp bandwidth. These two parameters

both affect the value of the op-amp current consumption.

Conventionally, these time parameters are predefined statically,

e.g. one third of the total settling time is reserved for slewing [5].

Using such an approach one of the settling regimes is dominant in

determining the current consumption. However it is shown here

that the small- and large-signal settling times can be chosen

dynamically so as to have the minimum possible current

consumption. The utilized algorithm can be applied to single-

stage and two-stage miller-compensated architectures as follows.

other

t

−

2/ (1)

For a single-pole op-amp or a two-pole op-amp where the second

pole is sufficiently larger than the unity-gain bandwidth, the

small- and large-signal settling times are related to the op-amp

characteristics as:

V

t

and

ss

nt.

τ==

SR

FS

ls=

udB

f

n

f

n

..2

1

β

.

2

1

.

3

ππ

=

−

(2,3)

where VFS is the full-scale signal range, f-3dB the -3-dB bandwidth,

β the feedback factor, fu the unity-gain bandwidth of the op-amp

and n the number of the time constants to be spent to achieve a

desired accuracy, equal to ln(1/ess). For a single-stage fully-

differential telescopic- or folded-cascode op-amp (Fig. 2), the

above-mentioned parameters can be related to the current of the

input devices by [6]:

loadi

FS

C

FS

SR

ls

I

V

/

V

t

==

and

load mi

ss

Cg

nt

/

1

.β

=

(4,5)

where SR is the op-amp slew rate, Ii is the current of the input

transistors, gmi is the trans-conductance of the input devices, and

Cload is the load capacitor at each output node. With the equation

expressed above, VFS is the single-ended voltage swing, half of the

differential full-scale voltage.

The required current of the input devices required to satisfy the

large- and small-signal settling criteria is therefore obtained from:

ls

t

load

C.

FS

i

V

I

=

and

ss

load

C

.

β

ieff

i

t

V

nI

2

.

.

,

=

(6,7)

where gmi=2Ii/Veffi and Veffi is chosen as the smallest effective

voltage that keeps the input transistors in the strong inversion

region and satisfies the other op-amp specifications such as gain.

If tls and tss are predefined statically [5], Ii should be chosen as the

maximum value of the above two, i.e.

=

ls

t

ss

loadieff

load FS

i

t

C

.

V

n

C.V

I

.2

.,max

,

β

(8)

leading to some power being wasted. However, if the two settling

contributions are determined dynamically such that the two above

terms for the current are equal, some power can be saved.

Therefore the optimum value for the bias current of the OTA

becomes:

+=∝

−

ss

β

FS

i eff

S

load

C

.

FS

optioptOTA

V.

Ve

2t

V

II

).ln(

1.22

,

1

,,

(9)

where tls+tss=tS (the total settling time). This equation shows the

dependency of the optimized current of a telescopic-cascode OTA

(or a folded-cascode OTA where the current value of the folded

branch is assumed proportional to that of the input branch) on the

load capacitor, the settling time and settling error, the full-scale

voltage and the feedback factor of the operational amplifier.

2.2 Expansion of the approach to other

structures

This relation will be still true even if gain-boosting amplifiers are

utilized [7] provided that the current consumption of those

amplifiers is proportional to the current of the main OTA. A

proportional closed-form formula can also be extracted if two-

stage Miller-compensated OTAs are used assuming that the

compensation capacitors are chosen equal to the load capacitors

and the current values in the second stages of the amplifier are

proportional to the currents of the input stages. Such an

assumption will be true when either the second stages currents are

high enough to satisfy the slewing requirements of the output

nodes, or class-A/AB amplifiers are used as the output stages [8].

The current values obtained with this relation are always smaller

than what obtained by the conventional methods. This power

saving can be sometimes considerably large compared to

conventional techniques where settling and slewing times are not

optimized.

2.3 The total current of the ADC OTAs

In order to express the total current of the OTAs in the entire

ADC versus the ADC parameters, the load capacitors seen by

each OTA should be calculated. Fig. 3 shows the m-bit residue

amplifier in a pipelined ADC. For an OTA used in the residue

stage shown in Fig. 3, the total capacitive load seen by the opamp

in the amplifying phase can be obtained from:

Vi+

Vi-

VDD

Ii

Vo-

CL-

Vo+

CL+

VSS

Vi+

Vi-

VDD

Vo-

CL-

Vo+

CL+

Ii

VSS

M1

M2

M5

M3

M4

(a) (b)

Figure 2. The (a) telescopic- and (b) folded-cascode

configurations

335

Page 3

opout compstagenext

F opS

F opS

load

CCC

CCC

CCC(

C

_

)

+++

++

+

=

−

(10)

where CF and CS are the feedback and sampling capacitors of the

amplifier and Cop is the input parasitic capacitance of the opamp.

Cnext-stage ,Ccomp and Cout_op are the input capacitance of the

following stage, the input capacitance of the comparators of the

following stage sub-ADC, and the output capacitance of the OTA,

respectively. It is instructive to note that when the jth residue

stage is in its hold mode, the (j+1)th stage is in sampling phase;

thus the input capacitor of that stage is obtained from:

+=

−

j

Sj stagenext

CC

1

1

11

2

,

+

+

++

=

j

j

j

F

m

F

CC

(11)

reminding that the ratio of the CS to the CF of each stage is 2m-1.

Vin

1

1

1

2

Vout

CS=(2m-1)CF

CF

Analog

MUX

Vr1

Vrp

m-bit

word

C1

C2

C2m-1

Vr1

Vr2

Vrp

Decoder

2

Figure 3. The schematic of the residue stage

Considering the fact that the number of required comparators for

an m-bit residue stage is “2mj-1” and for an mj-effective-bit residue

stage with one redundant bit is at least “21+mj-2”, the total load

capacitor of the jth OTA assuming bit redundancy is calculated

from:

op outcu

m

F

j

m

j

m

F

m

load

CCCCC

j

j

j

j

j

j

j

_

1

) 2

−

2 (

+

) 2 (

)1 2 (

2

1

1

1

+

+

+−

+=

+

+

+

+

γ

γ

(12)

where Ccu is the input capacitor of each comparator and γj

represents the ratio of Cop to CF. If the output capacitance

contribution is regarded as an excess value represented by the

excess coefficient ε, the load capacitance can be rewritten as:

cu

m

j

m

j

m

j

m

Fload

CCsC

j

j

j

j

jj

) 22 () 1 (

2

12

2

11

1

−++

+

−+

+=

++

+

ε

γ

γ

(13)

where the scaling factor of the jth stage, sj, is the ratio of the

capacitors of the j+1th stage and those of the jth stage ; i.e.

sj=Cj+1/Cj.

In this switched-capacitor amplifier, the feedback factor of the

OTA in the amplification phase, can be written as:

C

γ

β

+

=

++

=

m

opFS

F

CCC

2

1

(14)

Therefore the total current consumption of the OTAs in the n-

stage pipelined converter, using (9) for single-stage amplifiers can

be obtained from:

*

11

*

).(

]} ) 2 2 () 1 (

2

12

2 .[

.

2

)2 ().ln(

1{

2

*

1

1

1

1

OTA

cu

m

j

j

m

j

m

j

m

F

n

∑

j

FS

j

m

eff

ss

S

FS

OTAs

Inn

CsC

V

Ve

t

V

I

j

j

j

j

j

j

j

−+

−++

+

−+

+

+

+=

++

+

−

=

−

ε

γ

γ

γ

α

(15)

where α is the correction factor due to the extra current

consumption of the peripheral circuits such as the bias circuit. In

this equation, n* is the number of the stages in which the

capacitor scaling is performed reminding the fact that the scaling

stops as soon as the capacitors are determined by the minimum

required capacitor matching or the output parasitic capacitances

become dominant. The total contribution of the OTAs in the

current consumption of the converter is expressed versus the full-

scale voltage of the converter, the total settling time (a little

smaller than the sampling half-period), the minimum allowed

overdrive voltage of the input devices, the unit capacitor of the

first stage (CF1), the stage resolutions, scaling factors and finally

the input capacitor of the comparators. In the above equation it

has been assumed that the comparators used in different stages are

all similar. The problem can be easily generalized to a case where

different comparators are used for different stages.

Another important consideration is the sample-and-hold (S/H)

stage. The current consumption of this stage can be calculated in a

similar fashion with a resolution of m equal to zero. Just the

feedback factor of the OTA in the S/H amplifier should be

corrected due to the architecture utilized. For example for a flip-

around SHA architecture the feedback factor is smaller than unity

calculated form (14).

The total power consumption of the converter excluding the

power dissipated in the reference buffers and the digital error

correction and calibration blocks, can thus be obtained from (15)

plus the current consumption of the comparators, i.e.

n

m

I. ) 22 (

1

=

single comparator and mj is the number of effective bits resolved

by the jth stage. Note that the power dissipated in the OTAs and

the comparators is the major part of the total power consumption

of the ADC [2].

cu

j

j

1

∑

+

−

where Icu is the current consumption of a

3.

3.1 Input-referred noise of a residue stage

The input-referred thermal noise of a switched-capacitor amplifier

has two main sources, the on-resistance of the switches and the

operational amplifiers. It can be shown that the input-referred

noise due to switches in the switched-capacitor amplifier of Fig. 3

is obtained from [8]:

C

kTv

=

NOISE CALCULATIONS

2

2

ni

,

)(

2

FS

opFS

sw

CC

CC

+

++

(16)

Reminding that in an m-effective-bit residue stage (CS+CF)/CF=2m

and the ratio of Cop to CF is represented by γ then (16) can be

rewritten as:

336

Page 4

)22 .(

2

C

22

ni

,

mm

F

sw

kT

v

−−

+=γ

(17)

Besides, the input-referred thermal noise of a switched-capacitor

amplifier due to the operational amplifiers thermal noise is

dependent on the OTA architecture. With a fully-differential

single-stage OTA, the input-referred thermal noise of the residue-

amplifier due to the OTA noise can be obtained from [9]:

2

2

2

ni

,

1

42

+

⋅⋅⋅⋅=

FS

F

eq noise op

CC

C

BWFR kTv

β

(18)

In this equation F is the architecture-dependent excess noise

factor due to the non-input devices of the OTA. As an instance, in

the folded-cascode configuration of Fig. 2-b this factor is

calculated from:

1

5

1

2

1

m

m

m

m

g

g

g

g

F

++=

(19)

For a single-pole OTA or a two-pole structure where the second

pole is sufficiently larger than the unity-gain frequency, the

equivalent bandwidth can be obviously obtained from:

π

×=

eq

C22

and Rnoise=2/3gm1. Therefore the input-referred thermal noise of

the residue amplifier due to the OTA noise, can be expressed as:

β

π

×

load

m

g

BW

1

(20)

)22.(

3

4

22

ni

,

mm

load

op

C

kT

Fv

−−

+=γ

(21)

Hence, the total input-referred noise of the switched-capacitor

residue amplifier can be calculated from:

()

mm

Fload

residueni

C

kT

C

kT

Fv

22

,

222

3

4

−−

+

+=

γ

(22)

The same equation can be derived for a two-stage miller-

compensated OTA if the compensation capacitor is chosen equal

to the load capacitor.

3.2 Input-referred noise of the total ADC

In a pipelined A/D converter, the noise power of any stage when

referred to the input is divided by the power gains of the

preceding stages. Since the voltage gain of the ith residue

amplifier, Gi, is equal to 2mi , the total input referred noise of the

converter can be expressed as:

2

2

2 2,

1

.

∑

=

j

∑

=

j

∏

=

i

∑

=

j

∏

=

i

−

−

∑

=

i

−

===

++++=

n

m

n

n

j

m

n

n

j

i

n

1

n

n

n

n

t ni

j

i

j

i

jj

vv

G

v

G

.

G

.

G

v

GG

v

G

v

vv

1 2

2

2

1

1

1

2

2

1

1

2

2

2

3

2

2

2

1

2

2

2

2

1

2

1

1

1

4

3

2

2

...

(23)

The total input-referred noise of the converter will be therefore

calculated as:

+

=

j

1

()

∑

=

−−

∑

=

i

+

−

j

n

m

jm

j

jm

jFjload

tni

i

CC

F

kTv

2

,2,

,,

2,

1

1

2

22

2

3

4

γ

(24)

Making use of the relation derived for the load capacitor of the jth

stage, the above equation can be simply expressed versus the

values of the capacitors and the resolutions of stages when the

OTA configuration and therefore an estimation for the excess

noise factor F is known. When optimizing, the modification

parameters of εj and γj are primitively defined and then corrected

in a few iterations.

4. OPTIMIZATION METHODOLOGY

4.1 Design procedure

In the previous sections, closed-form equations for the total input-

referred noise and the optimized current consumption were

extracted as functions of the ADC capacitors and the resolutions

of the stages. Using MATLAB, a simple optimization CAD tool

has been developed by the authors to implement an optimization

problem of the form:

Find the optimum values of the capacitors and the resolutions of

different stages, in order to minimize the total power consumption

of the ADC, while the total input-referred noise requirement is

satisfied.

The main parameters of the sub-blocks of the converter including

the capacitor values and the resolutions of different stages are

simultaneously optimized while no limiting assumption is

imposed. It is only assumed here that the front-end stages are all

calibrated in order to meet the required accuracy of high-

resolution converters. Note that the calibration circuitry has

usually a negligible effect on the total power dissipation of the

converter. For the rms value of the required input-referred thermal

noise voltage one choice, employed here, is an equal value with

the quantization noise voltage calculated from

122

2

12

2

ni

N

ref

LSB

V

V

v

q

==

(25)

This choice will lead to 3dB degradation in the value of SNR of

the ideal ADC. Note that the signal-to-noise ratio is obtained

from:

=

10

log10

SNR

+

2

ni

2

ni

2

2/

thq

ref

vv

V

(26)

where Vref, the reference voltage, is equal to the single-ended full-

scale voltage swing. By using bit redundancy the maximum

comparator offset is permitted to be:

1

2

+

≤

m

ref

offset

V

V

(27)

where m is again the effective number of bits resolved by the

stage. Since the comparator offset must always meet the above

relation, after choosing a specific architecture for the comparators,

depending on the maximum input offset, the maximum allowed

resolution of the residue stages is determined.

The input parameters for tha CAD tool including N (the resolution

of the converter), Vref, Cmin (the minimum required value to satisfy

a specified matching behavior dependent on the fabrication

process), Ccu (the input capacitance of a single comparator), Icu

(the current dissipation of a single comparator), mmax (the

maximum permitted value for the resolution of a residue stage

337

Page 5

determined due to the maximum offset of the comparator), γr(the

vector of γi’s), εr(the vector of εi’s), F (the excess noise factor

dependent on the opamp architecture), and Veff (the minimum

value for the overdrive voltage of the input devices) should be

initially determined for the optimization tool. The optimization

tool will determine the optimum values for all capacitors, CF’s,

and the stage resolutions and also the optimum values for the bias

currents of the stages. The input transistors are then optimally

sized using the optimum values for the currents and the overdrive

voltages (Veff). It should be mentioned that some of the input

parameters such as the parameters of the comparators and if

permitted the reference voltage can be even optimally chosen

using the methodology presented here. Since the values of γr,

εrand F were just the initial estimations, a few iterations

accompanied with circuit simulations are required to modify the

optimized values of the parameters.

4.2 Design Examples

In order to illustrate the effectiveness of this methodology, a few

high-resolution examples are presented and compared with

conventional designs here.

Consider a 12-bit 3.3-V 50M-Samples/sec pipeline ADC. With a

full-scale voltage swing of 2Vp-p,diff (i.e. Vref=1V) that can be

conveniently realized using single-stage telescopic-cascode

opamps, the least-significant-bit (LSB) value is 2/212=488µV and

the optimization program suggests a resolution distribution of [3 2

1 1 1 1 1 2]. Note that the mentioned resolutions are the effective

number of bits and one redundant bit is generated in all stages.

The last stage only consists of three comparators to form a 2-bit

flash ADC [9]. It is assumed here that the required DC gain of

more than 72dB=212 for the first residue-stage operational

amplifier can be realized with such opamp configuration which is

verified by HSPICE simulation results using BSIM3v3 model

parameters of a 0.25µm CMOS process. Circuit simulations also

verified the settling behavior of the opamps. Assuming that the

minimum allowed capacitance to meet the matching requirements

is equal to 0.1pF, the feedback capacitors of different stages are

suggested as [0.5p 0.1p 0.1p … 0.1p]. The sampling capacitors

are chosen according to the required resolutions. In this problem

the current consumption of a single comparator with a dynamic

structure is assumed equal to 100uA.

Using the proposed approach, the total current consumption of the

opamps (including the current consumption of their bias circuits)

and the comparators of the converter is estimated to be 14mA. If

the converter was conventionally designed using 1.5-bit residue

stages such that the noise contribution allocated to each stage is

half of the previous one while the contribution of the first stage is

half of the total input-referred noise [10], then the scaling factors

of all stages should be chosen equal to 0.5 using identical

comparators, and to achieve similar SNR with the previous

example, the feedback capacitors of the stages would be [10p, 5p,

2.5p, 1.25p, 0.625p, …, 0.1p] and the total current consumption

of the OTAs and the comparators would be larger than 35mA! If

the resolution of the first stage is chosen equal to 2 effective bits

and all the following stages resolve 1.5 bits, the total current

consumption with the same scaling factors (i.e. 0.5) will become

25mA, again much larger than the optimized value. These

specifications were derived assuming no dedicated S/H stages

used in the front-end provided that the input signal changes less

than one LSB voltage of the first stage between the sampling

instance of the residue amplifier and the decision time of the sub-

ADC comparators. However, if a dedicated S/H stage is to be

used, the resolutions of the stages for the previous example

changes to [0 3 2 2 1 … 1 2] while the capacitor values will be as

what depicted in Fig. 4 changing from 4.2pF for the S/H stage to

0.5pF for the second stage and 0.1pF for the remaining stages.

Fig. 4 shows the current consumption of the OTA and the

comparators of different stages for two cases with and without the

S/H front-end stage. It can be seen that if the front-end S/H

amplifier is allowed to be omitted [11], considerable amount of

power will be saved. For converters with resolutions of not larger

than 10, the optimization CAD tool suggests a resolution of 1

effective bit (i.e. 1.5 bits) for all stages. This is exactly the same as

what proposed by Lewis [1] nevertheless the capacitor values are

optimized here. The developed tool can be used not only to

optimize an ADC but also to calculate the power consumption of

arbitrary design cases with specific values for the resolutions, the

capacitor values, the full-scale voltages, the comparator power

dissipations or the OTA noise excess factors. For example

consider a 12-bit converter with a supply voltage of 2.5V. The

designer can choose the maximum allowed number of bits per

stages, mmax, equal to 5 provided that low-offset power-hungry

comparators are utilized instead of dynamic structures with

usually higher offset voltages but with mmax of 3.

As another example, consider an ADC where the full-scale

(reference) voltage can be chosen by the designer (and is not

governed by the total system specifications). With a specific

supply voltage the optimization program can easily help the

designer to choose a two-stage opamp architecture (with higher

power and probably higher excess noise factor (F)) with a larger

full-scale voltage swing or a single-stage configuration with

smaller power dissipation for the opamps but with a smaller VFS

(of course provided that both opamps are able to meet the

required speed).

012345678

0

2

4

6

8

10

12

Stage Number

Current Consumption (mA)

with S&H

w/o S&H

0.45

0.25

0.1 0.1 0.10.1 0.1

4.2

0.5

0.3

Figure 4. The values of the current consumptions and the

capacitors of the stages (with and without the

dedicated SHA)

4.3 Power dependency on the ADC

specifications

Using the developed CAD tool the dependency of the total current

consumption of the ADC on the overall resolution and also the

full-scale voltage swing can be conveniently investigated. Fig. 5

shows the current consumption of the 50M-Samples/s converter

verses its resolution when dedicated sample-and-hold front-end

338