A lowpower design methodology for highresolution pipelined analogtodigital converters.
ABSTRACT In this paper a general method to design a pipelined ADC with minimum power consumption is presented. By expressing the total static power consumption and the total inputreferred noise of the converter as functions of the capacitor values and the resolutions of the converter stages, a simple optimization algorithm is employed to calculate the optimum values of these parameters, which lead to minimum power consumption while a. specified noise requirement is satisfied. To determine the bias current values of operational amplifiers, a novel optimal choice for settling and slewing time parameters is proposed applicable to both singlestage and twostage Millercompensated opamp, structures. Using the proposed methodology, the optimum values for capacitors, the resolutions and the opamp device sizes of all stages are determined in order to minimize the total power consumption. Design examples are presented and compared with conventional approaches to show the effectiveness of the proposed methodology.

Conference Paper: New SNDR enhancement techniques in pipelined ADC
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ABSTRACT: Signal to Noise and Distortion Ratio (SNDR) is widely chosen for dynamic characterization of ADC. For pipelined ADC in which the inner circuits' errors accumulate at the output, analysis of the origins of SNDR and its characterization can be very hard. However, due to a relationship between maximum INL of ADC and the distortion in its output codes, SNDR can be derived as a function of maximum INL value and its position in output codes. Utilizing this relationship, this paper develops two methods for SNDR enhancement that do not cost much power. The 50k sampled MonteCarlo simulation in the behavioral level indicates 75% increase in the possibility of having SNDR > 60db just by utilizing these two methods.Electrical Engineering (ICEE), 2013 21st Iranian Conference on; 01/2013  SourceAvailable from: payandehnia.com[Show abstract] [Hide abstract]
ABSTRACT: In this work the design of a low power 10bit 100MS/s pipeline ADC is presented. Low power consumption is realized by using an optimum bit per stage resolution and also by applying the correlated level shifting (CLS) technique for the first four stages. Moreover, by obviating the need for a first stage S/H, power consumption was reduced considerably. The first stage of the pipeline has a 2.5bit resolution, following six 1.5bit stages with a 2bit flash ADC at the end. For more power efficiency, stage scaling for the first three stages was also applied. Simulation results in HSPICE using a standard 0.18� m CMOS technology showed a SNDR and SFDR of 59.97dB and 64.8dB, respectively, for a 49.2MHz 2Vpp input signal. ADC power consumption excluding buffers and bondingpads is 6.67mW from a 1.8V supply voltage.Proceedings of the 24th Canadian Conference on Electrical and Computer Engineering, CCECE 2011, Niagara Falls, Ontario, Canada, 811 May, 2011; 01/2011 
Conference Paper: Indirect Miller effect based compensation in Low power twostage operational Amplifiers
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ABSTRACT: In this paper a novel compensation method for low power twostage operational Amplifiers is proposed. The proposed model is used 50 nm CMOS technology and employs a 50 femto Farad capacitor as the compensation capacitor. Although the method uses Miller effect compensation as the compensation method, the compensation capacitor plays its rule in an indirect way. The proposed method has simulated and the results has compared to the conventional cascode and an improved miller compensation miller compensationmodel. Simulation results show that the proposed method is made a proper stability, bandwidth and settling time, where the other methods are unstable in the same technology.Multimedia Computing and Systems (ICMCS), 2012 International Conference on; 01/2012
Page 1
A LowPower Design Methodology for HighResolution
Pipelined AnalogtoDigital Converters
Reza Lotfi Mohammad TaherzadehSani M.Yaser Azizi Omid Shoaei
ICDesign Lab., ECE Dept., University of Tehran,
North Kargar Ave., Tehran, I.R.Iran
Email: r.lotfi@ece.ut.ac.ir
ABSTRACT
In this paper a general method to design a pipelined ADC with
minimum power consumption is presented. By expressing the
total static power consumption and the total inputreferred noise
of the converter as functions of the capacitor values and the
resolutions of the converter stages, a simple optimization
algorithm is employed to calculate the optimum values of these
parameters, which lead to minimum power consumption while a
specified noise requirement is satisfied. To determine the bias
current values of operational amplifiers, a novel optimal choice
for settling and slewing time parameters is proposed applicable to
both singlestage and twostage Millercompensated opamp
structures. Using the proposed methodology, the optimum values
for capacitors, the resolutions and the opamp device sizes of all
stages are determined in order to minimize the total power
consumption. Design examples are presented and compared with
conventional approaches to show the effectiveness of the
proposed methodology.
Categories and Subject Descriptors
B.7.1 [Integrated circuits] Types and Design Styles VLSI (very
large scale integration)
General Terms
Design
Keywords
LowPower Design, Pipelined AnalogtoDigital Converters,
Operational Amplifiers
1. INTRODUCTION
Pipelining is one of the best approaches to implement highspeed
lowpower analogtodigital converters. Design approaches to
reduce the power consumption of pipelined ADCs are therefore of
great importance to realize mediumtohigh resolution highspeed
A/D converters with the least possible power consumption.
Several approaches have been proposed in literature for
systematic design of pipelined A/D converters. In [1] it has been
concluded that to minimize the power consumption of a pipelined
S/Hm1 bitsm2 bitsm3 bits2 bits
DIGITAL ERROR CORRECTION
2
N bits
ANALOG
INPUT
s0
scaling factor:
s1
s2
s3
m1+1
m2+1m3+1
Figure 1. The pipeline ADC structure
ADC, the resolution of all the stages can be chosen equal to 1.5
just in converters with resolutions of less than 10 bits. In [2] a
systematic design methodology has been proposed where
resolutions higher than 1.5 have been proposed for the frontend
stages of the highresolution converters but the capacitor values of
the stages are not optimized and a predefined noise distribution is
assumed. In [3] the effects of the capacitor scaling, parallelism,
and nonidentical resolutions per stages on the pipelined ADC
power consumption are investigated separately. In the latest
reported automatic design tool for pipelined ADCs [4] the
converter is optimized to minimize the power consumption and
area using geometric programming. However, the latter algorithm
is applied to a converter with identical resolution per stages. As
far as we understood it appears that neither of the proposed
approaches are as general yet simple as the approach proposed in
our work.
In this paper with no specific constraint, arbitrary capacitor
scaling as well as nonidentical resolution per each stage is
utilized in the design of the converter as shown in Fig. 1.
Effective equations are presented to optimally determine the
capacitor value and the resolution of each stage, in order to
minimize the power consumption of the converter, which makes
use of operational transconductance amplifiers (OTAs) with
optimized settling and slewing times.
First, a closedform equation for the bias current value of a single
stage or twostage Millercompensated opamp is derived
employing an innovative dynamic allocation of the small and
largesignal settling time parameters. Then the total static power
dissipation of the pipelined ADC is calculated. In section 3, the
total inputreferred noise of the converter is derived. Then a
design methodology is presented to minimize the power
consumption with a defined signaltonoise ratio (SNR). The
input parameters of the optimization CAD tool and related
considerations are addressed. Finally optimization examples
confirming the efficiency of the proposed methodology are
presented and the dependency of the power consumption on the
specifications of the converter is investigated.
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ISLPED ’03, August 2527, 2003, Seoul, Korea.
Copyright 2003 ACM 158113682X/03/0008…$5.00.
334
Page 2
2. OPTIMUM CURRENT OF THE OTA’S
2.1 Optimized bias current of a single OTA
In a switchedcapacitor circuit, the outputs of the operational
transconductance amplifiers have to settle to within a very small
fraction of their final values (ess), depending on the required
accuracy of the OTA, in a definite interval called the settling time.
The total settling time including the smallsignal (tss) and the
largesignal (tls) settling times should be less than half of the clock
period, i.e.
clk ls sss
Tttt
=+=
where tother is the rest of the halfperiod for nonoverlapping of
two clock pulses. While tls is due to the limited opamp slew rate,
tss depends on the finite opamp bandwidth. These two parameters
both affect the value of the opamp current consumption.
Conventionally, these time parameters are predefined statically,
e.g. one third of the total settling time is reserved for slewing [5].
Using such an approach one of the settling regimes is dominant in
determining the current consumption. However it is shown here
that the small and largesignal settling times can be chosen
dynamically so as to have the minimum possible current
consumption. The utilized algorithm can be applied to single
stage and twostage millercompensated architectures as follows.
other
t
−
2/ (1)
For a singlepole opamp or a twopole opamp where the second
pole is sufficiently larger than the unitygain bandwidth, the
small and largesignal settling times are related to the opamp
characteristics as:
V
t
and
ss
nt.
τ==
SR
FS
ls=
u dB
f
n
f
n
..2
1
β
.
2
1
.
3
ππ
=
−
(2,3)
where VFS is the fullscale signal range, f3dB the 3dB bandwidth,
β the feedback factor, fu the unitygain bandwidth of the opamp
and n the number of the time constants to be spent to achieve a
desired accuracy, equal to ln(1/ess). For a singlestage fully
differential telescopic or foldedcascode opamp (Fig. 2), the
abovementioned parameters can be related to the current of the
input devices by [6]:
loadi
FS
C
FS
SR
ls
I
V
/
V
t
==
and
load mi
ss
Cg
nt
/
1
.β
=
(4,5)
where SR is the opamp slew rate, Ii is the current of the input
transistors, gmi is the transconductance of the input devices, and
Cload is the load capacitor at each output node. With the equation
expressed above, VFS is the singleended voltage swing, half of the
differential fullscale voltage.
The required current of the input devices required to satisfy the
large and smallsignal settling criteria is therefore obtained from:
ls
t
load
C.
FS
i
V
I
=
and
ss
load
C
.
β
i eff
i
t
V
nI
2
.
.
,
=
(6,7)
where gmi=2Ii/Veffi and Veffi is chosen as the smallest effective
voltage that keeps the input transistors in the strong inversion
region and satisfies the other opamp specifications such as gain.
If tls and tss are predefined statically [5], Ii should be chosen as the
maximum value of the above two, i.e.
=
ls
t
ss
loadi eff
load FS
i
t
C
.
V
n
C.V
I
.2
.,max
,
β
(8)
leading to some power being wasted. However, if the two settling
contributions are determined dynamically such that the two above
terms for the current are equal, some power can be saved.
Therefore the optimum value for the bias current of the OTA
becomes:
+=∝
−
ss
β
FS
i eff
S
load
C
.
FS
opti optOTA
V.
Ve
2t
V
II
).ln(
1.22
,
1
,,
(9)
where tls+tss=tS (the total settling time). This equation shows the
dependency of the optimized current of a telescopiccascode OTA
(or a foldedcascode OTA where the current value of the folded
branch is assumed proportional to that of the input branch) on the
load capacitor, the settling time and settling error, the fullscale
voltage and the feedback factor of the operational amplifier.
2.2 Expansion of the approach to other
structures
This relation will be still true even if gainboosting amplifiers are
utilized [7] provided that the current consumption of those
amplifiers is proportional to the current of the main OTA. A
proportional closedform formula can also be extracted if two
stage Millercompensated OTAs are used assuming that the
compensation capacitors are chosen equal to the load capacitors
and the current values in the second stages of the amplifier are
proportional to the currents of the input stages. Such an
assumption will be true when either the second stages currents are
high enough to satisfy the slewing requirements of the output
nodes, or classA/AB amplifiers are used as the output stages [8].
The current values obtained with this relation are always smaller
than what obtained by the conventional methods. This power
saving can be sometimes considerably large compared to
conventional techniques where settling and slewing times are not
optimized.
2.3 The total current of the ADC OTAs
In order to express the total current of the OTAs in the entire
ADC versus the ADC parameters, the load capacitors seen by
each OTA should be calculated. Fig. 3 shows the mbit residue
amplifier in a pipelined ADC. For an OTA used in the residue
stage shown in Fig. 3, the total capacitive load seen by the opamp
in the amplifying phase can be obtained from:
Vi+
Vi
VDD
Ii
Vo
CL
Vo+
CL+
VSS
Vi+
Vi
VDD
Vo
CL
Vo+
CL+
Ii
VSS
M1
M2
M5
M3
M4
(a) (b)
Figure 2. The (a) telescopic and (b) foldedcascode
configurations
335
Page 3
op outcompstagenext
F opS
F opS
load
CCC
CCC
CCC(
C
_
)
+++
++
+
=
−
(10)
where CF and CS are the feedback and sampling capacitors of the
amplifier and Cop is the input parasitic capacitance of the opamp.
Cnextstage ,Ccomp and Cout_op are the input capacitance of the
following stage, the input capacitance of the comparators of the
following stage subADC, and the output capacitance of the OTA,
respectively. It is instructive to note that when the jth residue
stage is in its hold mode, the (j+1)th stage is in sampling phase;
thus the input capacitor of that stage is obtained from:
+=
−
j
Sjstagenext
CC
1
1
11
2
,
+
+
++
=
j
j
j
F
m
F
CC
(11)
reminding that the ratio of the CS to the CF of each stage is 2m1.
Vin
1
1
1
2
Vout
CS=(2m1)CF
CF
Analog
MUX
Vr1
Vrp
mbit
word
C1
C2
C2m1
Vr1
Vr2
Vrp
Decoder
2
Figure 3. The schematic of the residue stage
Considering the fact that the number of required comparators for
an mbit residue stage is “2mj1” and for an mjeffectivebit residue
stage with one redundant bit is at least “21+mj2”, the total load
capacitor of the jth OTA assuming bit redundancy is calculated
from:
opoutcu
m
F
j
m
j
m
F
m
load
CCCCC
j
j
j
j
j
j
j
_
1
) 2
−
2 (
+
) 2 (
)1 2 (
2
1
1
1
+
+
+−
+=
+
+
+
+
γ
γ
(12)
where Ccu is the input capacitor of each comparator and γj
represents the ratio of Cop to CF. If the output capacitance
contribution is regarded as an excess value represented by the
excess coefficient ε, the load capacitance can be rewritten as:
cu
m
j
m
j
m
j
m
Fload
CCsC
j
j
j
j
jj
) 22 ()1 (
2
12
2
11
1
−++
+
−+
+=
++
+
ε
γ
γ
(13)
where the scaling factor of the jth stage, sj, is the ratio of the
capacitors of the j+1th stage and those of the jth stage ; i.e.
sj=Cj+1/Cj.
In this switchedcapacitor amplifier, the feedback factor of the
OTA in the amplification phase, can be written as:
C
γ
β
+
=
++
=
m
opFS
F
CCC
2
1
(14)
Therefore the total current consumption of the OTAs in the n
stage pipelined converter, using (9) for singlestage amplifiers can
be obtained from:
*
11
*
).(
]}) 22 () 1 (
2
12
2.[
.
2
)2 ().ln(
1{
2
*
1
1
1
1
OTA
cu
m
j
j
m
j
m
j
m
F
n
∑
j
FS
j
m
eff
ss
S
FS
OTAs
Inn
CsC
V
Ve
t
V
I
j
j
j
j
j
j
j
−+
−++
+
−+
+
+
+=
++
+
−
=
−
ε
γ
γ
γ
α
(15)
where α is the correction factor due to the extra current
consumption of the peripheral circuits such as the bias circuit. In
this equation, n* is the number of the stages in which the
capacitor scaling is performed reminding the fact that the scaling
stops as soon as the capacitors are determined by the minimum
required capacitor matching or the output parasitic capacitances
become dominant. The total contribution of the OTAs in the
current consumption of the converter is expressed versus the full
scale voltage of the converter, the total settling time (a little
smaller than the sampling halfperiod), the minimum allowed
overdrive voltage of the input devices, the unit capacitor of the
first stage (CF1), the stage resolutions, scaling factors and finally
the input capacitor of the comparators. In the above equation it
has been assumed that the comparators used in different stages are
all similar. The problem can be easily generalized to a case where
different comparators are used for different stages.
Another important consideration is the sampleandhold (S/H)
stage. The current consumption of this stage can be calculated in a
similar fashion with a resolution of m equal to zero. Just the
feedback factor of the OTA in the S/H amplifier should be
corrected due to the architecture utilized. For example for a flip
around SHA architecture the feedback factor is smaller than unity
calculated form (14).
The total power consumption of the converter excluding the
power dissipated in the reference buffers and the digital error
correction and calibration blocks, can thus be obtained from (15)
plus the current consumption of the comparators, i.e.
n
m
I. ) 22 (
1
=
single comparator and mj is the number of effective bits resolved
by the jth stage. Note that the power dissipated in the OTAs and
the comparators is the major part of the total power consumption
of the ADC [2].
cu
j
j
1
∑
+
−
where Icu is the current consumption of a
3.
3.1 Inputreferred noise of a residue stage
The inputreferred thermal noise of a switchedcapacitor amplifier
has two main sources, the onresistance of the switches and the
operational amplifiers. It can be shown that the inputreferred
noise due to switches in the switchedcapacitor amplifier of Fig. 3
is obtained from [8]:
C
kTv
=
NOISE CALCULATIONS
2
2
ni
,
)(
2
FS
opFS
sw
CC
CC
+
++
(16)
Reminding that in an meffectivebit residue stage (CS+CF)/CF=2m
and the ratio of Cop to CF is represented by γ then (16) can be
rewritten as:
336
Page 4
)22.(
2
C
22
ni
,
mm
F
sw
kT
v
−−
+=γ
(17)
Besides, the inputreferred thermal noise of a switchedcapacitor
amplifier due to the operational amplifiers thermal noise is
dependent on the OTA architecture. With a fullydifferential
singlestage OTA, the inputreferred thermal noise of the residue
amplifier due to the OTA noise can be obtained from [9]:
2
2
2
ni
,
1
42
+
⋅⋅⋅⋅=
FS
F
eqnoise op
CC
C
BWFR kTv
β
(18)
In this equation F is the architecturedependent excess noise
factor due to the noninput devices of the OTA. As an instance, in
the foldedcascode configuration of Fig. 2b this factor is
calculated from:
1
5
1
2
1
m
m
m
m
g
g
g
g
F
++=
(19)
For a singlepole OTA or a twopole structure where the second
pole is sufficiently larger than the unitygain frequency, the
equivalent bandwidth can be obviously obtained from:
π
×=
eq
C22
and Rnoise=2/3gm1. Therefore the inputreferred thermal noise of
the residue amplifier due to the OTA noise, can be expressed as:
β
π
×
load
m
g
BW
1
(20)
)22 .(
3
4
22
ni
,
mm
load
op
C
kT
Fv
−−
+=γ
(21)
Hence, the total inputreferred noise of the switchedcapacitor
residue amplifier can be calculated from:
()
mm
F load
residueni
C
kT
C
kT
Fv
22
,
222
3
4
−−
+
+=
γ
(22)
The same equation can be derived for a twostage miller
compensated OTA if the compensation capacitor is chosen equal
to the load capacitor.
3.2 Inputreferred noise of the total ADC
In a pipelined A/D converter, the noise power of any stage when
referred to the input is divided by the power gains of the
preceding stages. Since the voltage gain of the ith residue
amplifier, Gi, is equal to 2mi , the total input referred noise of the
converter can be expressed as:
2
2
22,
1
.
∑
=
j
∑
=
j
∏
=
i
∑
=
j
∏
=
i
−
−
∑
=
i
−
===
++++=
n
m
n
n
j
m
n
n
j
i
n
1
n
n
n
n
tni
j
i
j
i
jj
vv
G
v
G
.
G
.
G
v
GG
v
G
v
vv
1 2
2
2
1
1
1
2
2
1
1
2
2
2
3
2
2
2
1
2
2
2
2
1
2
1
1
1
4
3
2
2
...
(23)
The total inputreferred noise of the converter will be therefore
calculated as:
+
=
j
1
()
∑
=
−−
∑
=
i
+
−
j
n
m
jm
j
jm
jFjload
tni
i
CC
F
kTv
2
,2,
,,
2,
1
1
2
22
2
3
4
γ
(24)
Making use of the relation derived for the load capacitor of the jth
stage, the above equation can be simply expressed versus the
values of the capacitors and the resolutions of stages when the
OTA configuration and therefore an estimation for the excess
noise factor F is known. When optimizing, the modification
parameters of εj and γj are primitively defined and then corrected
in a few iterations.
4. OPTIMIZATION METHODOLOGY
4.1 Design procedure
In the previous sections, closedform equations for the total input
referred noise and the optimized current consumption were
extracted as functions of the ADC capacitors and the resolutions
of the stages. Using MATLAB, a simple optimization CAD tool
has been developed by the authors to implement an optimization
problem of the form:
Find the optimum values of the capacitors and the resolutions of
different stages, in order to minimize the total power consumption
of the ADC, while the total inputreferred noise requirement is
satisfied.
The main parameters of the subblocks of the converter including
the capacitor values and the resolutions of different stages are
simultaneously optimized while no limiting assumption is
imposed. It is only assumed here that the frontend stages are all
calibrated in order to meet the required accuracy of high
resolution converters. Note that the calibration circuitry has
usually a negligible effect on the total power dissipation of the
converter. For the rms value of the required inputreferred thermal
noise voltage one choice, employed here, is an equal value with
the quantization noise voltage calculated from
122
2
12
2
ni
N
ref
LSB
V
V
v
q
==
(25)
This choice will lead to 3dB degradation in the value of SNR of
the ideal ADC. Note that the signaltonoise ratio is obtained
from:
=
10
log10
SNR
+
2
ni
2
ni
2
2/
thq
ref
vv
V
(26)
where Vref, the reference voltage, is equal to the singleended full
scale voltage swing. By using bit redundancy the maximum
comparator offset is permitted to be:
1
2
+
≤
m
ref
offset
V
V
(27)
where m is again the effective number of bits resolved by the
stage. Since the comparator offset must always meet the above
relation, after choosing a specific architecture for the comparators,
depending on the maximum input offset, the maximum allowed
resolution of the residue stages is determined.
The input parameters for tha CAD tool including N (the resolution
of the converter), Vref, Cmin (the minimum required value to satisfy
a specified matching behavior dependent on the fabrication
process), Ccu (the input capacitance of a single comparator), Icu
(the current dissipation of a single comparator), mmax (the
maximum permitted value for the resolution of a residue stage
337
Page 5
determined due to the maximum offset of the comparator), γr(the
vector of γi’s), εr(the vector of εi’s), F (the excess noise factor
dependent on the opamp architecture), and Veff (the minimum
value for the overdrive voltage of the input devices) should be
initially determined for the optimization tool. The optimization
tool will determine the optimum values for all capacitors, CF’s,
and the stage resolutions and also the optimum values for the bias
currents of the stages. The input transistors are then optimally
sized using the optimum values for the currents and the overdrive
voltages (Veff). It should be mentioned that some of the input
parameters such as the parameters of the comparators and if
permitted the reference voltage can be even optimally chosen
using the methodology presented here. Since the values of γr,
εrand F were just the initial estimations, a few iterations
accompanied with circuit simulations are required to modify the
optimized values of the parameters.
4.2 Design Examples
In order to illustrate the effectiveness of this methodology, a few
highresolution examples are presented and compared with
conventional designs here.
Consider a 12bit 3.3V 50MSamples/sec pipeline ADC. With a
fullscale voltage swing of 2Vpp,diff (i.e. Vref=1V) that can be
conveniently realized using singlestage telescopiccascode
opamps, the leastsignificantbit (LSB) value is 2/212=488µV and
the optimization program suggests a resolution distribution of [3 2
1 1 1 1 1 2]. Note that the mentioned resolutions are the effective
number of bits and one redundant bit is generated in all stages.
The last stage only consists of three comparators to form a 2bit
flash ADC [9]. It is assumed here that the required DC gain of
more than 72dB=212 for the first residuestage operational
amplifier can be realized with such opamp configuration which is
verified by HSPICE simulation results using BSIM3v3 model
parameters of a 0.25µm CMOS process. Circuit simulations also
verified the settling behavior of the opamps. Assuming that the
minimum allowed capacitance to meet the matching requirements
is equal to 0.1pF, the feedback capacitors of different stages are
suggested as [0.5p 0.1p 0.1p … 0.1p]. The sampling capacitors
are chosen according to the required resolutions. In this problem
the current consumption of a single comparator with a dynamic
structure is assumed equal to 100uA.
Using the proposed approach, the total current consumption of the
opamps (including the current consumption of their bias circuits)
and the comparators of the converter is estimated to be 14mA. If
the converter was conventionally designed using 1.5bit residue
stages such that the noise contribution allocated to each stage is
half of the previous one while the contribution of the first stage is
half of the total inputreferred noise [10], then the scaling factors
of all stages should be chosen equal to 0.5 using identical
comparators, and to achieve similar SNR with the previous
example, the feedback capacitors of the stages would be [10p, 5p,
2.5p, 1.25p, 0.625p, …, 0.1p] and the total current consumption
of the OTAs and the comparators would be larger than 35mA! If
the resolution of the first stage is chosen equal to 2 effective bits
and all the following stages resolve 1.5 bits, the total current
consumption with the same scaling factors (i.e. 0.5) will become
25mA, again much larger than the optimized value. These
specifications were derived assuming no dedicated S/H stages
used in the frontend provided that the input signal changes less
than one LSB voltage of the first stage between the sampling
instance of the residue amplifier and the decision time of the sub
ADC comparators. However, if a dedicated S/H stage is to be
used, the resolutions of the stages for the previous example
changes to [0 3 2 2 1 … 1 2] while the capacitor values will be as
what depicted in Fig. 4 changing from 4.2pF for the S/H stage to
0.5pF for the second stage and 0.1pF for the remaining stages.
Fig. 4 shows the current consumption of the OTA and the
comparators of different stages for two cases with and without the
S/H frontend stage. It can be seen that if the frontend S/H
amplifier is allowed to be omitted [11], considerable amount of
power will be saved. For converters with resolutions of not larger
than 10, the optimization CAD tool suggests a resolution of 1
effective bit (i.e. 1.5 bits) for all stages. This is exactly the same as
what proposed by Lewis [1] nevertheless the capacitor values are
optimized here. The developed tool can be used not only to
optimize an ADC but also to calculate the power consumption of
arbitrary design cases with specific values for the resolutions, the
capacitor values, the fullscale voltages, the comparator power
dissipations or the OTA noise excess factors. For example
consider a 12bit converter with a supply voltage of 2.5V. The
designer can choose the maximum allowed number of bits per
stages, mmax, equal to 5 provided that lowoffset powerhungry
comparators are utilized instead of dynamic structures with
usually higher offset voltages but with mmax of 3.
As another example, consider an ADC where the fullscale
(reference) voltage can be chosen by the designer (and is not
governed by the total system specifications). With a specific
supply voltage the optimization program can easily help the
designer to choose a twostage opamp architecture (with higher
power and probably higher excess noise factor (F)) with a larger
fullscale voltage swing or a singlestage configuration with
smaller power dissipation for the opamps but with a smaller VFS
(of course provided that both opamps are able to meet the
required speed).
012345678
0
2
4
6
8
10
12
Stage Number
Current Consumption (mA)
with S&H
w/o S&H
0.45
0.25
0.10.10.10.1 0.1
4.2
0.5
0.3
Figure 4. The values of the current consumptions and the
capacitors of the stages (with and without the
dedicated SHA)
4.3 Power dependency on the ADC
specifications
Using the developed CAD tool the dependency of the total current
consumption of the ADC on the overall resolution and also the
fullscale voltage swing can be conveniently investigated. Fig. 5
shows the current consumption of the 50MSamples/s converter
verses its resolution when dedicated sampleandhold frontend
338