Conference Paper

A low-power design methodology for high-resolution pipelined analog-to-digital converters.

IC-Design-Lab., Univ. of Tehran, Iran
DOI: 10.1109/LPE.2003.1231890 Conference: Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003
Source: DBLP

ABSTRACT In this paper a general method to design a pipelined ADC with minimum power consumption is presented. By expressing the total static power consumption and the total input-referred noise of the converter as functions of the capacitor values and the resolutions of the converter stages, a simple optimization algorithm is employed to calculate the optimum values of these parameters, which lead to minimum power consumption while a. specified noise requirement is satisfied. To determine the bias current values of operational amplifiers, a novel optimal choice for settling and slewing time parameters is proposed applicable to both single-stage and two-stage Miller-compensated opamp, structures. Using the proposed methodology, the optimum values for capacitors, the resolutions and the opamp device sizes of all stages are determined in order to minimize the total power consumption. Design examples are presented and compared with conventional approaches to show the effectiveness of the proposed methodology.

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    • "The first two steps aiming at determining the stage resolution and capacitor scaling will be discussed below in detail. Then the current of each stage and the possible architecture of SHA and comparator should be decided in consideration of the capacitor mismatch, thermal noise and finite gain from OTA that have been discussed in [5]. After accomplishing the procedures mentioned above, it is necessary to verify the performance of overall prototype. "
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    • "In general the techniques used to improve energy efficiency can be broken down into three levels. The lowest is at the circuit level were bias currents and component values are optimized [5]. The next level of abstraction is to change the ADC architecture. "
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    • "To be able to express the total input-referred noise power of the converter, the total input-referred noise power of an individual stage, consisting of the noise due to the on-resistances of the switches and the noise due to the OTAs, is calculated and then referred to the input of the converter by dividing by the power gains of the preceding stages [5] [6]. The optimum values of the capacitors and simultaneously the resolutions of all the stages are determined in order to minimize the power consumption. "
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    ABSTRACT: In this paper, a very low-power high-speed high-resolution pipelined analog-to-digital converter (ADC) based on an optimization methodology previously proposed by the authors, is presented. By expressing the total static power consumption and the total input-referred noise of the converter as function of the capacitor values and the resolutions of the converter stages, a simple optimization algorithm is employed to calculate the optimum values of these parameters, which lead to minimum power consumption while a specified noise requirement is satisfied. Design considerations and simulation results of the 12-bit 3.3V 40MS/s pipelined ADC with only 56mW consumption in a 0.25μm CMOS process, are presented. The simulated values of the SNR and SFDR are 69dB and 75dB respectively.
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