High speed Fp multipliers and adders on FPGA platform.
ABSTRACT The paper proposes high speed FPGA implementations of adders and multipliers in Fp. The work shows through experimental results that due to optimized addition chain available in such devices, Karatsuba decomposition upto a particular level improves the performance. Further the paper modifies existing interleaved multiplier using Montgomery ladder and the high speed adder circuits. Extensive experiments have been performed. The result shows that the proposed design provides 70% speedup from the best known designs.
- SourceAvailable from: K. Pekmestzi
Conference Proceeding: FPGA-based Design of a Large Moduli Multiplier for Public-Key Cryptographic Systems[show abstract] [hide abstract]
ABSTRACT: High secure cryptographic systems require large bit-length encryption keys which presents a challenge to their efficient hardware implementation especially in embedded devices. Modular multiplication is the core operation in well known cryptosystems like RSA and elliptic curve (ECC). Therefore, it is important to employ efficient modular multiplications techniques to improve the overall performance of the cryptographic system. We present a modular multiplier based on the ordinary Montgomery's multiplication algorithm and a new array multiplication scheme to perform the multiplication. The new modular multiplier is scalable and can be used for large bit-lengths. We also implement the modular multiplier into the Virtex4 FPGA devices and we show that our technique has better performance when compared with other schemes. To implement large bit-length multiplications we used a novel partitioning and pipeline folding scheme to fit at least 512-bit modular multiplications on a single FPGA.Computer Design, 2006. ICCD 2006. International Conference on; 11/2007
Conference Proceeding: A scalable dual mode arithmetic unit for public key cryptosystems[show abstract] [hide abstract]
ABSTRACT: Elliptic curve cryptosystems (ECC) have become popular in recent years due to their smaller key sizes than traditional public key schemes such as RSA. However the gap between the sizes of these systems is increasing as security requirements become more demanding due to cryptanalytic advances. At current security levels of 80 bits, the corresponding key sizes for ECC and RSA are J60 and 1,024 bits respectively. Although the ECC key size is attractive for embedded applications, the popularity of RSA means that it will remain in legacy applications for the foreseeable future. This paper proposes a dual mode arithmetic unit capable of supporting the underlying field operations performed by both the ECC and RSA public key schemes. A hardware optimized version of the Montgomery algorithm is employed to perform modular multiplication efficiently. The disparity in key sizes is addressed by combining the dual processors to operate in parallel for ECC or in a pipelined series for RSA.Information Technology: Coding and Computing, 2005. ITCC 2005. International Conference on; 05/2005
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ABSTRACT: Montgomery multiplication in GF(2<sup>m</sup>) is defined by a(x)b(x)r<sup>-1</sup>(x) mod f(x), where the field is generated by a root of the irreducible polynomial f(x), a(x) and b(x) are two field elements in GF(2<sup>m</sup>), and r(x) is a fixed field element in GF(2 <sup>m</sup>). In this paper, first, a slightly generalized Montgomery multiplication algorithm in GF(2<sup>m</sup>) is presented. Then, by choosing r(x) according to f (x), we show that efficient architectures of bit-parallel Montgomery multiplier and squarer can be obtained for the fields generated with an irreducible trinomial. Complexities of the Montgomery multiplier and squarer in terms of gate counts and time delay of the circuits are investigated and found to be as good as or better than that of previous proposals for the same class of fieldsIEEE Transactions on Computers 06/2002; 51(5):521-529. · 1.38 Impact Factor