Conference Paper

A Reconfigurable Applcation Specific Instruction Set Processor for Viterbi and Log-MAP Decoding.

Technische Universität Kaiserslautern, Kaiserlautern, Rheinland-Pfalz, Germany
DOI: 10.1109/SIPS.2006.352570 Conference: Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2006, Proceedings, October 2-4, 2006, Banff, Alberta, Canada
Source: DBLP

ABSTRACT Future mobile and wireless communications networks require flexible modem architectures with high performance. This paper presents a dynamically reconfigurable application specific instruction set processor (dr-ASIP) for the application domain of channel coding in wireless communications systems: FlexiTreP. It features Viterbi and Log-MAP decoding for support of binary convolutional codes and binary as well as duobinary turbo codes. The FlexiTreP can support more than 10 current wireless communication standards. Furthermore, its flexibility allows for adaptation to future systems. It consists of a specialized pipeline and a dedicated communication and memory infrastructure. Simulation and synthesis results obtained for Log-MAP and Viterbi applications demonstrate maximum throughput of 200 and 133 Mbps, respectively

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