Conference Paper

Low-Power Content Addressable Memory With Read/Write and Matched Mask Ports.

DOI: 10.1007/978-3-540-74442-9_8 Conference: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings
Source: DBLP


A low-power content addressable memory (CAM) with read/write and mask match ports is proposed. The CAM cell is based on the
conventional 6T cross-coupled inverters used for storing data with an addition of two NMOS transistors for reading out. In
addition, the CAM has another four transistors for mask comparison operation through classical pre-charge operation. The read-out
port exploits a pre-charge reading mechanism in order to alleviate the drawback of power consumption generated from sensing
amplifiers and all other related synchronization circuits which are structured in every column in the memory. Thus, the read
and match features can have concurrent operations. An experimental CAM structure of storage size 64-bit x 128-bit is designed
using 0.18-μm CMOS single poly and three layers of metals measuring a cell die area of 24.4375 μm2 and a total silicon area of 0.269192 mm2. The circuit works up to 200 MHz in simulation with total power consumption of 0.016 W at 1.8-V supply voltage.

5 Reads
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: A read-static-noise-margin-free SRAM cell consists of seven transistors, several of which are low-V, NMOS transistors used to achieve both low-V<sub>dd</sub> and high-speed operation. A 64 kb SRAM macro is fabricated in 90 nm CMOS technology. Both a minimum V<sub>dd</sub> of 440 mV and a 20 ns access time with a 0.5 V supply are obtained.
    Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International; 03/2005
  • [Show abstract] [Hide abstract]
    ABSTRACT: This paper presents a novel VLSI architecture for high-speed data compressor designs which implement the well-known LZ77 algorithm. The architecture mainly consists of three units, namely content addressable memory, match logic, and output stage. The content address memory generates a set of hit signals which identify those positions whose symbols in a specified window are the same as input symbol. These hits signals are then passed to the match logic which determines one matched stream and its match length and location in the window to form the kernel of compressed data. These two items are then passed to the output stage for packetization before sent out. By trading off hardware complexity and compression ratio, 2KB window size and adjustable maximum match length are considered in our proto-type VLSI chip. Simulation results show that, based on a 0.8 μm CMOS process technology, clock speed up to 50 MHz can be achieved. This implies that the developing data compressor chip can handle many real-life applications such as in video coding and high-speed data storage systems
    Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on; 06/1994
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: SRAM cell stability will be a primary concern for future technologies due to variability and decreasing power supply voltages. 6T-SRAM can be optimized for stability by choosing the cell layout, device threshold voltages, and the β ratio. 8T-SRAM, however, provides a much greater enhancement in stability by eliminating cell disturbs during a read access, thus facilitating continued technology scaling. We demonstrate the smallest 6T (0.124μm<sup>2</sup> half-cell) and full 8T (0.1998μm<sup>2</sup>) cells to date.
    VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on; 07/2005

Shadi MS Harb, Ph.D