Power and Area Optimization of 3D Networks-on-Chip Using Smart and Efficient Vertical Channels.
ABSTRACT 3D NoC offers greater device integration, faster vertical interconnects and more power efficient inter-layer communication due to the beneficial attribute of short through silicon via (TSV) in 3D IC technologies. However, TSV pads used for bonding to a wafer layer, occupy significant chip area and result in routing congestions and expensive manufacturing process. This can lead to a significant reduction in 3D ICs' yield and higher power densities compared to 2D NoCs. In this paper, a power-efficient and low-cost inter-layer communication scheme is proposed as one way to mitigate these challenges. Instead of using a pair of unidirectional channels for inter-layer communication, utilizing a high-performance bidirectional channel enables a system to benefit from low-latency nature of the vertical interconnects and to remarkably reduce the number of TSVs. Additionally, we present a forecasting-based dynamic frequency scaling technique for reducing the power consumption of the inter-layer communication. Our extensive simulations demonstrate significant area and power improvements compared to a typical symmetric 3D NoC.
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ABSTRACT: Shorter global interconnects enable 3D NoC structures to offer higher performance, improved packaging density, and lower interconnect power consumption to CMPs and SoCs compared to their 2D counterparts. However, substantial challenges such as high peak temperatures, power densities and area footprints of vertical interconnects in each layer cannot be ignored. In this paper, a power and area efficient 3D NoC architecture based on power-aware Bidirectional Bisynchronous Vertical Channels (BBVC) is proposed as a solution to mitigate these challenges. Instead of using a pair of unidirectional channels for inter-layer communication, utilizing a dynamically self-configurable BBVC enables a system to benefit from low-latency nature of the vertical interconnects. In addition, based on the GALS implementation approach of the proposed channels, a forecasting-based dynamic frequency scaling technique for reducing the power consumption of the inter-layer communication is introduced. Simulation results show that the proposed architecture can reduce up to 47% through-silicon via (TSV) area footprint and up to 18% NoC power consumption with a slight performance degradation compared to a typical Symmetric 3D NoC.Journal of Computer and System Sciences 06/2013; 79(4):440–456. · 1.00 Impact Factor
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ABSTRACT: Through Silicon Via (TSV) is the state-of-the-art vertical interconnect technology in three dimensional Integrated Circuits (3D-ICs). TSVs offer short wire length with low capacitive load and, hence, fast connections between two or more chip layers. On the other hand, TSVs consume a relative large amount of chip area and are error prone during manufacturing resulting in a dramatic yield drop for large TSV counts. Because of their short wire length, TSVs can be clocked much higher than conventional intra-layer links. To efficiently utilize the vertical bandwidth of TSVs, this paper proposes multiplexing several virtual links with dynamically allocated bit rates for guaranteed service connections via a shared TSV-Hub-Array. Virtual links can be state-of-the-art interconnects like busses, crossbars or 2D-NoC links. The TSV-Hub allows migration of traditional 2D interconnects towards the 3D stack while benefiting from a reduced TSV count and reuse of existing IP blocks and interconnection schemes. Furthermore, the TSV-Hub approach is also advantageous under interconnect resilience considerations. An incorporated switchbox enables dynamic protection switching for several faulty TSVs. Moreover, it can even cope with situations when more than the number of spare TSVs becomes defective. By means of a case study with two independent AXI interconnects, we could show an area reduction in the range of at least 10% for a TSV size of 10 μm and conservatively estimated the reliability improvement by one order of magnitude in comparison to a direct link interconnection.Microprocessors and Microsystems 01/2013; 37(8):823–835. · 0.55 Impact Factor