Conference Paper

# A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits.

DOI: 10.1007/978-3-540-74442-9_15 Conference: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings

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**ABSTRACT:**Variability in digital integrated circuits makes timing ver- ication an extremely challenging task. In this paper, a canonical rst order delay model is proposed that takes into account both correlated and independent randomness. A novel linear-time block-based statistical timing algorithm is employed to propagate timing quantities like arrival times and required arrival times through the timing graph in this canonical form. At the end of the statistical timing, the sensitivities of all timing quantities to each of the sources of variation are available. Excessive sensitivities can then be targeted by manual or automatic optimization methods to improve the robustness of the design. The statistical timing analysis is incremental, and is therefore suitable for use in the inner loop of physical synthesis or other optimization programs. The second novel contribution of this paper is the computation of local and global criticality probabilities. For a very small cost in CPU time, the probability of each edge or node of the timing graph being critical is computed. These criticality probabilities provide additional useful diag- nostics to synthesis, optimization, test generation and path enumeration programs. Numerical results are presented on industrial ASIC chips with over two million logic gates.IEEE Trans. on CAD of Integrated Circuits and Systems. 01/2006; 25:2170-2180. - [Show abstract] [Hide abstract]

**ABSTRACT:**Not AvailableProceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004; 01/2004 - Operations Research. 01/1961; 9(2):145-162.

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