Low Power Single Electron Or/Nor Gate Operating at 10GHz.
ABSTRACT The design and simulation of a single-electron OR/NOR gate is being presented using a Monte Carlo based tool. Both the OR/NOR behavior and the stability were verified while the free energy behavior of the circuit was also examined. The results confirmed that the circuit behaved as an OR/NOR gate, depicting improved characteristics than previously published single electron OR circuits, achieving a really fast operational speed at low power. Moreover, the noise through the circuit was nearly diminished, while a stable behavior of the circuit was verified without any noise present at the output points.
- SourceAvailable from: Nikos Konofaos[show abstract] [hide abstract]
ABSTRACT: In this paper, we present a single-electron 2-4 decoder built using single-electron devices. The circuit is designed using a proper tool based on a Monte Carlo technique. First a single-electron AND gate is studied and then the 2-D decoder circuit is designed and studied. The results proved that the circuit was a 2-4 decoder, while the behaviour of the free energy of the system (which was calculated to be 4.90×10−1 eV) and the stability diagram verified the correct functioning of the circuit.Microelectronics Journal. 01/2008;
Article: Single-electron OR gate[show abstract] [hide abstract]
ABSTRACT: The design of a single-electron OR gate is presented. Bits of information are represented by the presence or absence of single electrons at a conducting island. The static operation and the stability of this gate are analysed using Monte Carlo simulationElectronics Letters 04/2000; · 1.04 Impact Factor
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ABSTRACT: A physically based compact analytical single electron transistor (SET) model is proposed for hybrid CMOS-SET analog circuit simulation. The modeling approach is based on the "orthodox theory" of single electron tunneling, and valid for single or multi gate, symmetric or asymmetric devices and can also explain the background charge effect. The model parameters are physical device parameters and an associated parameter extraction procedure is reported. The device characteristics produced by the proposed model are verified with Monte Carlo simulation for large range of drain to source voltages (|V<sub>DS</sub>|≤3e/C<sub>Σ</sub>) and temperatures [T≤e<sup>2</sup>/(10k<sub>B</sub>C<sub>Σ</sub>)] and good agreements are observed. The proposed model is implemented in a commercial circuit simulator in order to develop a computer-aided design framework for CMOS-SET hybrid IC designs. A series of SPICE simulations are successfully carried out for different CMOS-SET hybrid circuits in order to reproduce their experimental/Monte Carlo simulated characteristics.IEEE Transactions on Electron Devices 12/2004; · 2.06 Impact Factor