LOW POWER SINGLE ELECTRON OR/NOR GATE
OPERATING AT 10GHz
T. Tsiolakis and G. Ph. Alexiou
Dept. of Computer Engineering & Informatics,
University of Patras
Patras, GR-26500 Greece,
Dept. Information & Communications Systems Engineering
University of the Aegean
Karlovassi Samos, GR-83200 Greece,
may drive the electron outside the island. Hence, the necessary
Abstract—the design and simulation of a single-electron
OR/NOR gate is being presented using a Monte Carlo based tool.
Both the OR/NOR behavior and the stability were verified while
the free energy behavior of the circuit was also examined. The
results confirmed that the circuit behaved as an OR/NOR gate,
depicting improved characteristics than previously published
single electron OR circuits, achieving a really fast operational
speed at low power. Moreover, the noise through the circuit was
nearly diminished, while a stable behavior of the circuit was
verified without any noise present at the output points.
Index Terms— Circuit free energy, circuit stability, Coulomb
blockade, Monte Carlo method, single electron gate, single
electron design and simulation, single electron transistor (SET),
single electron tunneling, single electronics, noise.
Single-electronics technology (SET), which is based on the
fundamental physical principle of the tunnelling effect through
a Coulomb blockade, seems to be a very promising
nanoelectronic technology [1, 2]. During the last five years,
several single-electronics circuits that combine large integration
and low power dissipation have been published and analysed,
such as logic gates, adders, decoders and several more [3-7].
Recently, hybrid structures have been proposed, making CMOS
and SET technologies more compatible [8-10]. The key
elements of such circuits are the fundamental gates which are
built using single-electron logic.
The basic physics behind the design, construction and
functioning of the single-electron logic are based on the
concept of a phenomenon called the Coulomb blockade. This
can be described as follows: Consider an electrical neutral
small conductor, which is called an island or a node, having
exactly as many electrons as it has protons in its crystal lattice.
This neutral island does not generate any appreciable electric
field beyond its borders and an additional electron located
outside the island can be brought into it by a weak external
force. The energy to charge an island with an electron is called
the Coulomb energy (Ec) and is given by:
where C is the capacitance of the island. Though the extra
charge in the island is very small, the electric field generated by
this charge is inversely proportional to the square of the island
size and may became very strong in nanoscale structures. This
strong electric field inhibits further electron transfer into the
island, giving thus rise to the Coulomb blockade effect.
Single electronics exploits the Coulomb blockade by
representing bits of information by the presence or absence of a
single electron at conducting islands. In order to keep an extra
electron confined into an island the Coulomb energy must be
greater than the thermal energy, otherwise thermal fluctuations
where kB is Boltzmann’s constant and T is the absolute
The basic principle of single-electronics is that one needs
Coulomb energy Ec to charge an island with an electron.
Electrons tunnel independently from island to island through
tunnel junctions. To assure that electron states are localized on
islands all tunnel resistances must be larger than the
where h is Planck’s constant.
Figure 1. The designed OR/NOR gate.
To simulate the tunnelling of electrons from island to island
in a single-electron circuit one has to determine the rates of all
possible tunnel events. The tunnel rate of a possible tunnel
event depends on the change in the circuit’s free energy caused
by this particular event. The free energy, F, of a single-electron
circuit is the difference of the electrostatic energy, U, stored in
2010 IEEE Annual Symposium on VLSI
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its capacitances and the work done by the voltage sources of
the circuit, W:
is the summary of each work done by the n voltage sources of
the circuit, and the electrostatic energy U, stored in its
capacitances is given by:
where, q and υ are the unknown parts of the island charge and
voltage matrices, and Q and V are the known parts of the
island charge and voltage matrices, respectively.
This paper demonstrates a complementary OR/NOR gate
capable to work in low temperature in a stable matter. The aim
of this work is to present such a circuit that is suitable for use
in more complex circuits than those presented so far and with
better and superior performance. In particular, this article
examines possible advantages of the new design in the metrics
most important for single-electron circuits, namely, the noise
margins for device parameters at a fixed operation
temperature, in this case at 4 K. Moreover, low free energy,
stability and complementarity, especially for circuits as
complex as multiplexers are essential parts of a quality design.
Hence, the need to design effective, complementary gates with
low noise and stable operation has emerged. In the following
paragraphs, we present such a task using a Monte Carlo based
tool  and compare with other similar gate designs
appearing in the literature . In the final paragraphs we
conclude the benefits of the design which are concentrated on
the low power, the high speed, the diminished noise, and the
stable operation of the circuit in a network of gates.
II. CIRCUIT DESIGN AND SIMULATION
Figure 1 depicts the circuit of the proposed OR/NOR gate.
The circuit comprises of 6 junctions. Junctions J1-J4 are
identical, with their resistance being equal to 105 Ohm.
Junction J5 has a resistance of 2.6 x 104 Ohm, while J6 has a
large resistance of 1014 Ohm in order to prevent electron
transport from the ground. The Vdd voltage is constant at 0.1 V.
The two inputs (Input1 and Input2) can only take two values,
one equal to 0.0 V, which corresponds to the logic ‘1’, and the
other equal to -0.1 V, which corresponds to the logic ‘0’. These
inputs are applied to islands N1 and N2 through the capacitors
C1 and C2, which are identical, having a capacitance equal to
10-18 F each. The gate has two complementary output points,
the islands N3 and N4 respectively. The presence of a positive
charge in one of these islands corresponds to the logic ‘1’,
whereas the absence of a positive charge corresponds to the
logic ‘0’. Among the other elements of the circuit, the
capacitors C3 and C4 improve the performance of the OR gate
and offer its complementary output, hence becoming the vital
elements of transforming the circuit into a NOR/OR gate. Their
existence, especially for C4, depends on the whole circuit
layout in which this logic gate is considered to be part of it.
The values of their capacitance are identical and equal to10-18 F
Using SIMON , the gate was tested for its operation
characteristics. Figure 2 depicts the inputs and the
complementary outputs of the gate. In particular, figures 2a
and 2b show the “Input1” and “Input2” input signals, whereas
figures 2c and 2d show the time variation at nodes N3 (2c)
denoted as “Output~” and N4 (2d) denoted as “Output” which
correspond to either a reading of logic “0” or to a reading of
logic “1”, always with respect to the lower and upper values.
It is concluded from the output signals that exactly one
electron is allowed to leave the output nodes providing the
positive charge at the output nodes of one electron. This offers
compatibility with previously published circuits. Indeed, the
depicted behavior is that of an OR/NOR gate, with node N4
providing the OR function and node N3 providing its NOR
complementary function. When both “Input1” and “Input2” are
equal to -0.1V, hence the input vector [0,0] is applied, N3 is
charged positively, because an electron from N3 travels to the
voltage source. Hence N3=1 and N4=0 in charge terms. Then,
if any other vector is applied, an electron jumps from N4 to N3
and the situation becomes N4=1 and N3=0. This happens every
time the outputs change while the island N3 is discharged via
N4 and the island N4 is discharged via the ground. All of the
above verify the NOR/OR functioning of the circuit.
Figure 2. The inputs and the complementary outputs of the gate.
Figure 3 depicts the free energy history diagram which is
used to test and verify the proper operation of the circuit. The
free energy of the designed circuit is calculated at each step of
an electron path, starting either from the ground, an island or a
voltage source, and ending at the ground, at an island or at a
voltage source respectively. The results are plotted as energy
versus time or time steps. This plot allows the calculation of
the total free energy [1-5] of the circuit, during a time period
of 1 sec, while the input vectors are applied as shown in figure
2. It has to be mentioned here that this time period is virtual,
because SIMON offers quasi time simulation (11). For real
time simulation we use another tool later in this paper.
Therefore, the free energy calculation can be made as:
14 . 0
where ti is the ith time step, resulting a quite low value.
Further than that, the plot in figure 3, depicts a stable
operation of the circuit, with an energy behavior as predicted
by the theory for single electron circuits, verifying the validity
of the designed gate.
To confirm this stable operation of the circuit, the stability
plot of the OR/NOR gate has been constructed and it is shown
in figure 4. Each point of this Cartesian space corresponds to a
combination of input voltage values. The free energy of the
circuit is calculated at each point of the stability plot. Points
that correspond to local minima of the circuit’s free energy are
colored white. Therefore, at these points, the corresponding
combination of input voltage values prohibits electron
tunneling, hence keeping the electrons into the islands. On the
other hand, points that correspond to local maxima of the
circuit’s free energy are colored black and are unstable points.
For these points, the corresponding combination of input
voltage values enhances electron tunneling and the number of
electrons into the islands can not be clearly determined.
Figure 3. The free energy diagram of the gate.
Figure 4. The stability diagram of the gate at the temperature of 4 K.
The vertices A, B, C and D of the square drawn on the
stability plot correspond to the applied vectors at the input
points. As shown, the transition of the output from low to high
and vice versa, does not drive the gate to instability or local
However, a significant temperature increment drives these
gates to instability as it does in most Single Electron Circuits,
so any other operating temperatures but values near the
absolute zero are not yet recommended for these circuits. The
present circuit has been simulated for different values of
temperature and the results showed that it can achieve an
optimum performance at a temperature of 4 K.
Another design and simulation tool similar to SIMON is
the so called SECS . A major difference between them is
that SECS offers real time simulation. For the extraction of an
operational speed we took notice of the time that is necessary
for a Coulomb effect to occur and the gate as tested can
operate very well at 10GHz. In SECS the simulation system
incorporates the stochastic nature of tunneling into its model
using the Monte Carlo method. We may not know exactly
when a tunnel event will occur, but we can determine, through
a probability distribution and via random sampling, the time
interval until the next tunnel event. The circuit presented here
can perform very well and without any change at its output or
any noise addition at all at 10 GHZ as a result of its good
Figure 5 shows the rise and fall times and the propagation
delay of the gate. As shown the rise and fall times of both the
complementary outputs are equal to 1.5x10-13sec. The lower
part of the picture depicts the input transition from the logical
low to the logical high value. We have chosen this transition to
be a linear one in order to be more realistic. The time needed
for the gate to completely obtain a constant value until the
input starts to change is 10-12 sec while the time the time
needed for the output to begin changing until the end of the
inputs transition is 1.4x10-13 sec. Therefore the results are more
than satisfactory. However the events that occur in each
simulation run are randomized so the propagation delay may
vary between 0.5x10-12 and 2.5x10-12 sec.
Comparing with similar designs appearing in the literature,
the closest circuit is the one proposed by Karafyllidis . In
order to do so, we first calculated the free energy of our circuit
in the same way as that in the circuit depicted in .
Therefore, we need to apply the same sequence of the applied
input vectors over time as that in  with respect to the lower
and upper values. Doing so, we achieve
This value is substantially lower than that which is
calculated for the same function of the circuit in , which
was equal to 0.396 eV, thus an approximately 80% reduction
is calculated for our circuit.
Finally, the output noise of the OR gate that was present in
the circuit presented in , has been vanished in our case due
to the stability of the circuit. In more detail, the noise has been
diminished due to the small changes of the free energy during
the outputs transitions compared to that appearing in .
Table I summarizes the comparison between the circuit
presented here and the one depicted in . The values depicted
for the various parameters have been all calculated under the
Figure 5. Speed simulation of the circuit.
CIRCUIT CHARACTERISTICS AND COMPARISON.
Circuit Characteristics Circuit in  Circuit in this work
Voltage input for logic 1 (V)
Voltage input for logic 0 (V)
Free energy (eVx10-1)
In this article, the design and simulation of a single
electron OR/NOR gate was presented and analysed using the
Monte Carlo based tool known as SIMON. The proposed
circuit has proven its complementary functioning, it showed a
very low energy consumption value and a stable operation for
a temperature of 4K. Its operating frequency was been
determined using a real time Monte Carlo simulator known as
SECS. The noise at the outputs was minimised and a stable
operation was achieved for the whole operation. This kind of
gate is suitable for use in complex circuits and it is a well
improved design compared with similar ones appearing in the
Future work involves the design of complex circuits using
these complementary gates, such as multiplexers.
 K. Likharev: “Single-electron devices and their applications”, Proc.
IEEE 87, pp. 606–632, 1999.
 C. Wasshuber: “Computational Single-Electronics (Computational
Microelectronics)”, Springer, New York, 2001.
 G. Zardalidis, I. Karafyllidis: “Design and simulation of a nanoelectronic
single-electron control—not gate”, Microelectron. J., 37, pp. 94–97,
 I. Tsimperidis, I. Karafyllidis, A. Thanailakis: “A single-electron three
input AND gate”, Microelectron. J., 33, pp. 191–195, 2002.
 I. Karafyllidis, “Single-electron OR gate,” Electron. Lett., 36, pp. 407–
 G. Zardalidis, I. Karafyllidis: “A single-electron full adder”, IEE Proc.
Circuits, Dev. Syst., 150, pp. 173–177, 2003.
 T. Tsiolakis, N. Konofaos, G. Ph. Alexiou: “Design, simulation and
performance evaluation of
Microelectronics Journal 39(12), pp. 1613-1621, 2008.
 B. H. Lee, Y. H. Jeong: “A Novel SET/MOSFET Hybrid Static Memory
Cell Design”, IEEE Trans. Νanotech., 3, pp. 377-382, 2004.
 S. Mahapatra, V. Vaish, C. Wasshuber, K. Banerjee, K. Ionescu:
“Analytical Modeling of Single Electron Transistor for Hybrid CMOS-
SET Analog IC Design”, IEEE Trans. Electr. Dev. 51, pp. 1772-1782,
 A. Venkataratnam, A. K. Goel: “Design and simulation of logic circuits
with hybrid architectures of single-electron transistors and conventional
MOS devices at room temperature”, Microelectronics Journal 39 (12),
pp. 1461-1468, 2008.
 C. Wasshuber, H. Kosina, S. Selberherr: “SIMON-a simulator for single-
electron tunnel devices and circuits,” IEEE Trans. Computer-Aided
Design 16, pp. 937–944, 1997.
 G. Zardalidis, I. Karafyllidis "SECS: A new single electron circuit
simulator", IEEE Transactions on Circuits and Systems I, vol. 55, no 9,
a single-electron 2-4 decoder”,