Conference Paper

Corona: System Implications of Emerging Nanophotonic Technology

Univ. of Wisconsin - Madison, Madison, WI
DOI: 10.1109/ISCA.2008.35 Conference: 35th International Symposium on Computer Architecture (ISCA 2008), June 21-25, 2008, Beijing, China
Source: DBLP

ABSTRACT We expect that many-core microprocessors will push performance per chip from the 10 gigaflop to the 10 teraflop range in the coming decade. To support this increased performance, memory and inter-core bandwidths will also have to scale by orders of magnitude. Pin limitations, the energy cost of electrical signaling, and the non-scalability of chip-length global wires are significant bandwidth impediments. Recent developments in silicon nanophotonic technology have the potential to meet these off- and on-stack bandwidth requirements at acceptable power levels. Corona is a 3 D many-core architecture that uses nanophotonic communication for both inter-core communication and off-stack communication to memory or I/O devices. Its peak floating-point performance is 10 teraflops. Dense wavelength division multiplexed optically connected memory modules provide 10 terabyte per second memory bandwidth. A photonic crossbar fully interconnects its 256 low-power multithreaded cores at 20 terabyte per second bandwidth. We have simulated a 1024 thread Corona system running synthetic benchmarks and scaled versions of the SPLASH-2 benchmark suite. We believe that in comparison with an electrically-connected many-core alternative that uses the same on-stack interconnect power, Corona can provide 2 to 6 times more performance on many memory intensive workloads, while simultaneously reducing power.

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Available from: Marco Fiorentino, Aug 21, 2015
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    • "The NoC employs the multiple-write-single-read (MWSR) mechanism for L1-to-L2 communication with a dedicated silicon-photonic channel having a width of 512 bits for each L2 cache bank. A token-based protocol is used to arbitrate between the L1 caches for getting access to L1-to-L2 communication channels [5]. Tokens are assigned in a round-robin fashion for fairness. "
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    ABSTRACT: In manycore systems, the silicon-photonic link technology is projected to replace electrical link technology for global communication in network-on-chip (NoC) as it can provide as much as an order of magnitude higher bandwidth density and lower data-dependent power. However, a large amount of fixed power is dissipated in the laser sources required to drive these silicon-photonic links, which negates any bandwidth density advantages. This large laser power dissipation depends on the number of on-chip silicon-photonic links, the bandwidth of each link, and the photonic losses along each link. In this paper, we propose to reduce the laser power dissipation at runtime by dynamically activating/deactivating L2 cache banks and switching ON/OFF the corresponding silicon-photonic links in the NoC. This method effectively throttles the total on-chip NoC bandwidth at runtime according to the memory access features of the applications running on the manycore system. Full-system simulation utilizing Princeton application repository for shared-memory computers and Stanford parallel applications for shared-memory-2 parallel benchmarks reveal that our proposed technique achieves on an average 23.8% (peak value 74.3%) savings in laser power, and 9.2% (peak value 26.9%) lower energy-delay product for the whole system at the cost of 0.65% loss (peak value 2.6%) in instructions per cycle on average when compared to the cases where all L2 cache banks are always active.
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 06/2015; 34(6):972 - 985. DOI:10.1109/TCAD.2015.2402172 · 1.20 Impact Factor
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    • "In a Multiple-Writer-Single-Reader [24] (MWSR) crossbar every router reads from its own bus, and writes on the other routers' busses (Figure 2). Because lasers can be built within a waveguide [14], Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. "
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    ABSTRACT: The high-speed and low-cost modulation of light make photonic interconnects an attractive solution for the communication de-mands of manycore processors. However, the high optical loss of many nanophotonic components results in high laser power consumption, most of which is wasted during periods of system inactivity. We propose EcoLaser, an adaptive laser control mechanism that saves between 24-77% of the laser power by turning off the laser when not needed. These power savings allow the cores to exploit a higher power budget and achieve speedups of 1.1-2x.
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    • "In this paper we scale the alloptical network suggested by Li et al. [2] and compute the overhead of reliability management to compensate variations. We compare two techniques: Thermal tuning and channel hopping (widely used in optical network design [4]) and our proposed reliability management technique. We use a multiprocess workload of a 64-thread of " lu " running on our cores. "
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    ABSTRACT: Intercore communication in many-core processors presently faces scalability issues similar to those that plagued intracity telecommunications in the 1960s. Optical communication promises to address these challenges now, as then, by providing low latency, high bandwidth, and low power communication. Silicon photonic devices presently are vulnerable to fabrication and temperature-induced variability. Our fabrication and measurement results indicate that such variations degrade interconnection performance and, in extreme cases, the interconnection may fail to function at all. In this paper, we propose a reliability-aware design flow to address variation-induced reliability issues. To mitigate effects of variations, limits of device design techniques are analyzed and requirements from architecture-level design are revealed. Based on this flow, a multilevel reliability management solution is proposed, which includes athermal coating at fabrication-level, voltage tuning at device-level, as well as channel hopping at architecture-level. Simulation results indicate that our solution can fully compensate variations thereby sustaining reliable on-chip optical communication with power efficiency.
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