Conference Paper

Express virtual channels: Towards the ideal interconnection fabric

DOI: 10.1145/1250662.1250681 Conference: 34th International Symposium on Computer Architecture (ISCA 2007), June 9-13, 2007, San Diego, California, USA
Source: DBLP


ABSTRACT Due to wire delay scalability and bandwidth,limitations inherent in shared buses and dedicated links, packet-switched on-chip interconnection networks are fast emerging as the pervasive communication fabric to connect dieren t processing elements in many-core chips. However, current state-ofthe-art packet-switched networks rely on complex routers which increases the communication overhead and energy consumption as compared,to the ideal interconnection fabric. In this paper, we try to close the gap between the stateof-the-art packet-switched network and the ideal interconnect by proposing express virtual channels (EVCs), a novel o w control mechanism which allows packets to virtually bypass intermediate routers along their path in a completely non-speculative fashion, thereby lowering the energy/delay towards that of a dedicated wire while simultaneously approaching ideal throughput with a practical design suitable for on-chip networks. Our evaluation results using a detailed cycle-accurate simulator on a range of synthetic trac,and SPLASH benchmark traces show upto 84% reduction in packet latency and upto 23% improvement in throughput while reducing the average router energy consumption by upto 38% over an existing state-of-the-art packet-switched design. When compared to the ideal interconnect, EVCs add just two cycles to the no-load latency, and are within 14% of the ideal throughput. Moreover, we show that the proposed design incurs a minimal hardware overhead while exhibiting excellent scalability with increasing network sizes.

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Available from: Partha Kundu, Oct 16, 2015
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    • "Transmitting data in NoCs is mainly in the form of data package causes high latency when the competition for transfer channel communicating in different nodes. In order to provide low latency and high bandwidth communication in NoCs fast router is proposed in [4] [5] [6] and new network topologies are proposed in [7] [8] [9]. "
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    ABSTRACT: To reduce traffic jam caused by various data competitions for channel, we present a low delay and energy efficient network-on-chip with three channels for different type’s data. Hence, the transmission for control data between cores won’t be congested by the big amount of data transmitted from caches to core, and it achieves better performance in latency and energy. Our strategy is to make a directive long wire to connect two nodes in the same row or column, and distribute these connective wires to different layers which are connected by 3D stacking technology. In the many-core system applied with this topology, every pair of core-cache nodes are at most 5 hops away while real-time and short control information is transmitted by a 2D mesh network. The experimental results show up to 23% of network latency reduction and up to 15% energy reduction when compared to a 3D network-on-chip.
    12/2013; 12(12). DOI:10.11591/telkomnika.v11i12.2764
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    • "The SWIFT NoC implements such an approach, based on TFC [8], as shown in Fig. 2(c). TFC [8] has been shown to be better than other approaches like express virtual channels (EVC) [9] as it allows flits to chain together tokens to form arbitrarily long bypass paths with turns, while EVC only allowed bypassing within a dimension upto a maximum of three-hops. Other approaches to tackle buffer power include adding physical links to bypass intermediate routers [20], or using link repeaters as temporary buffers [4], [19], [21] to reduce buffers within the router. "
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    ABSTRACT: A 64-bit, 8 × 8 mesh network-on-chip (NoC) is presented that uses both new architectural and circuit design techniques to improve on-chip network energy-efficiency, latency, and throughput. First, we propose token flow control, which enables bypassing of flit buffering in routers, thereby reducing buffer size and their power consumption. We also incorporate reduced-swing signaling in on-chip links and crossbars to minimize datapath interconnect energy. The 64-node NoC is experimentally validated with a 2 × 2 test chip in 90 nm, 1.2 V CMOS that incorporates traffic generators to emulate the traffic of the full network. Compared with a fully synthesized baseline 8 × 8 NoC architecture designed to meet the same peak throughput, the fabricated prototype reduces network latency by 20% under uniform random traffic, when both networks are run at their maximum operating frequencies. When operated at the same frequencies, the SWIFT NoC reduces network power by 38% and 25% at saturation and low loads, respectively.
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems 08/2013; 21(8):1432-1446. DOI:10.1109/TVLSI.2012.2211904 · 1.36 Impact Factor
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    • "Most of today's chip prototypes, as well as virtual channel routers, are covered by ORION 2.0 models. In addition, different topologies, e.g., flattened butterfly [12], express virtual channel [15], etc. can be easily explored using ORION 2.0 models. In general, any topology that uses wormhole routers is supported by ORION 2.0 models; more significantly several router microarchitectures such as token flow control router [14] have been modeled using different subcomponents of ORION 2.0 models. "
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    ABSTRACT: As industry moves towards multicore chips, networks-on-chip (NoCs) are emerging as the scalable fabric for interconnecting the cores. With power now the first-order design constraint, early-stage estimation of NoC power has become crucially important. In this work, we present ORION 2.0, an enhanced NoC power and area simulator, which offers significant accuracy improvement relative to its predecessor, ORION 1.0.
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems 02/2012; 20(1-20):191 - 196. DOI:10.1109/TVLSI.2010.2091686 · 1.36 Impact Factor
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