On-line SVM traffic classification.
ABSTRACT A wide range of traffic classification approaches has been proposed in the last few years by the scientific community. However, the development of complete classification architectures that work directly in real-time on high capacity links is limited. In this paper we present the implementation of a machine-learning technique (SVM), one of the most accurate but most computationally expensive mechanisms, on the CoMo project infrastructure. We show the computational time required to process different traffic traces and the optimization steps we adopted to improve the performance of the system and achieve real-time classification on high-speed links.
Conference Paper: Hardware Acceleration of SVM-Based Traffic Classification on FPGA[Show abstract] [Hide abstract]
ABSTRACT: Understanding the composition of the Internet traffic has many applications nowadays, mainly tracking bandwidth consuming applications, QoS-based traffic engineering and lawful interception of illegal traffic. Although many classification methods such as Support Vector Machines (SVM) have demonstrated their accuracy, not enough attention has been paid to the practical implementation of lightweight classifiers. In this paper, we consider the design of a real-time SVM classifier at many Gbps to allow online detection of categories of applications. Our solution is based on the design of a hardware accelerated SVM classifier on a FPGA board.IWCMC TRAC 2012: 3rd International Workshop on TRaffic Analysis and Classification, Limassol, Cyprus; 08/2012
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ABSTRACT: Analyzing the composition of Internet traffic has many applications nowadays, like tracking bandwidth-consuming applications, QoS-based traffic engineering and lawful interception of illegal traffic. Even though many flow-based classification methods, such as Support Vector Machines (SVM) have demonstrated their accuracy, few practical implementations of lightweight classifiers exist. We consider in this paper the design of a real-time SVM traffic classifier at hundreds of Gb/s to allow online detection of categories of applications. We also implement a high-speed flow reconstruction algorithm able to handle one million concurrent flows. The solution is based on the massive parallelism and low-level network interface access of FPGA boards. We find maximum supported bit rates up to 408 Gb/s for classification and up to 20 GB/s for flow reconstruction for the most challenging trace. Results are confirmed using a commercial Combov2 board with a Virtex 5 FPGA.