Automated Resource-Aware Floorplanning of Reconfigurable Areas in Partially-Reconfigurable FPGA Systems.
DOI: 10.1109/FPL.2011.104 Conference: International Conference on Field Programmable Logic and Applications, FPL 2011, September 5-7, Chania, Crete, Greece
The floor planning activity is a key step in the design of systems on FPGAs, but the approaches available today rarely consider both the constraints imposed by the heterogeneous distribution of the resources in the devices and the reconfiguration capabilities. In fact, current-generation FPGAs present a complex architecture, but also offer more sophisticated reconfiguration features. The proposed floor planner, based on an accurate model of the devices, takes into account all these elements and finds an optimal solution, suitable for reconfigurable designs.
Conference Paper: TaBit: a Framework for Task Graph to Bitstream Generation[Show abstract] [Hide abstract]
ABSTRACT: Nowadays, the usual embedded design flow makes use of different tools to perform the several steps required to obtain a running application on a reconfigurable platform. The integration among these tools is usually not fully automated, forcing the developer to take care of these intermediate steps. This process slows down the application development and delays its time to market. In this work we present the TaBit framework, intended for FPGA designers, that is able to guide the developer from the original partitioned application, described as a task graph, down to its deployment onto the target device. Moreover, this framework defines a set of interfaces that allows the developer to integrate custom scheduling and floor placing techniques. The framework takes care of the integration between the different steps and, based on the designer inputs, it is able to automatically generate a software Scheduling Engine and the set of bitstreams ready to be deployed onto the target device.Proceedings of IEEE IC-SAMOS'12 - Embedded Computer Systems: Architectures, MOdeling, and Simulation - July 16-19, 2012 - Samos, Greece; 01/2012
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ABSTRACT: The FASTER project aims to ease the definition, implementation and use of dynamically changing hardware systems. Our motivation stems from the promise reconfigurable systems hold for achieving better performance and extending product functionality and lifetime via the addition of new features that work at hardware speed. This is a clear advantage over the more straightforward software component adaptivity. However, designing a changing hardware system is both challenging and time consuming. The FASTER project will facilitate the use of reconfigurable technology by providing a complete methodology that enables designers to easily specify, analyse, implement and verify applications on platforms with general-purpose processors and acceleration modules implemented in the latest reconfigurable technology. To better adapt to different application requirements, the tool-chain will support both region-based and micro-reconfiguration and provide a flexible run-time system that will efficiently manage the reconfigurable resources. We will use applications from the embedded, high performance computing, and desktop domains to demonstrate the potential benefits of the FASTER tools on metrics such as performance, power consumption and total ownership cost.Digital System Design (DSD), 2012 15th Euromicro Conference on; 01/2012
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ABSTRACT: The exploitation of the capabilities offered by reconfigurable architectures is traditionally a demanding task due to the intrinsic time consuming and error prone customization of these systems around the specific application. Moreover, existing approaches are not able to integrate the notion of partial and dynamic reconfiguration (PDR) from the early stages of the decision phases, potentially leading to sub-optimal solutions. In this work, we propose SMASH (Simultaneous Mapping and Scheduling with Heuristics), a highly automated design methodology focused on explicitly taking into account PDR during the design of reconfigurable designs. It combines heuristics for both the design of the architecture and the mapping and scheduling of the partitioned application. We show how this additional degree of freedom leads to architectures whose performance are improved with respect to the baseline.Rapid System Prototyping (RSP), 2013 International Symposium on; 01/2013
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