Conference Paper

Massively Parallel/Reconfigurable Emulation Model for the D-algorithm.

DOI: 10.1007/3-540-46117-5_134 Conference: Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings
Source: DBLP


In this paper, we propose an approach to test generation based on reconfigurable devices, emulators, and Field Programmable
Gate Arrays (FPGA). This approach is based on automatically designing a circuit which implements the D-algorithm specialized
for the circuit under test. This approach exploits fine-grain parallelism in the forward/ backward implications, and conflict
checking. In this paper, we show an implementation with a lower hardware overhead than previous approaches making this technique
more attractive.

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