High-Level Partitioning of Digital Systems Based on Dynamically Reconfigurable Devices.
ABSTRACT This paper presents a high-level temporal partitioning algorithm, which is able to split the VHDL description of a digital
system into two equivalent subdescriptions. The primary goal of the algorithm is to obtain two area-balanced, time-independent
partitions. The descriptions of these partitions can be separately simulated, synthesized and implemented as different configurations
of a dynamically reconfigurable device. The partitioning principle is based on a directed task hypergraph. Each vertex of
this hypergraph corresponds to one concurrent assignment of the description being analysed. The resources required for the
physical implementation of each vertex are calculated by means of a simplified resource estimator. Time dependencies between
vertices are denoted by hyperedges representing signals connecting appropriate concurrent assignments.
Conference Paper: FIGARO - an automatic tool flow for designs with dynamic reconfiguration[Show abstract] [Hide abstract]
ABSTRACT: Although runtime partial dynamic reconfiguration of FPGAs has been researched for many years and there have been a few FPGAs equipped with the required architectural features, it has yet to achieve general recognition by the commercial design community. This is mainly due to the lack of a professional CAD tool support. This paper presents extended concepts from E. L. Horta et al. (2002), Xilinx Application Note 290 (2004) and I. Robertson et al. (2002) implemented in a placement and routing tool. The tool supports creation of partially dynamically reconfigurable designs from input EDIF files and user-specified reconfiguration schedule down to bitstream generation for FPGAs that support this technology, such as the Atmel AT40K and AT94K series.Field Programmable Logic and Applications, 2005. International Conference on; 09/2005
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ABSTRACT: This paper presents a framework for building and modeling a new-generation self-adaptive systems. The rst part of the paper pro- poses an architecture of a self-adaptive networked entity that forms the basic element of the approach. The second part describes a modeling en- vironment based on Matlab / Simulink and one possible implementation of the self-adaptive networked entity. A physical realization of the pro- posed system is demonstrated on the computation of a simple FIR lter in several FPGAs acting as hardware in the loop in Matlab / Simulink.Evolvable Systems: From Biology to Hardware, 8th International Conference, ICES 2008, Prague, Czech Republic, September 21-24, 2008. Proceedings; 01/2008