Crosstalk noise dominates in deep submicron VLSI design as interconnects are more closely placed over a small layout area. Signal response and signal integrity is largely affected by crosstalk delay and noise. In this paper, we propose a coupled line delay model for on-chip interconnects during global routing, with crosstalk between wires as the parameter to be optimized. Our proposed model is influenced by moment matching model of a transmission line. We propose an algorithm for crosstalk aware delay tree construction, optimizing the effect of crosstalk delay in the tree structure by employing a cut and join strategy. Experiments are done on some benchmark instances with different technology parameters, and simulation results obtained are quite encouraging.
[Show abstract][Hide abstract] ABSTRACT: The dominance of interconnect delay in VLSI circuit de- sign is well-known. Construction of routing trees in recent times has to take care of the timing issues for faster design convergence. Thus there is immense scope of research in design and performance of interconnects. Our current work encompasses two aspects of this research. On one hand, we consider the construction of cost-effective global routing trees with the recently introduced Y -interconnects, and on the other hand, we utilize this framework for verifying the supremacy of the Elmore delay estimate for its high fidelity. In order to ensure accurate computation of fidelity, (i) we propose new statistically proven formulae for fidelity, and (ii) compute the fidelity values based on delay estimates for optimal and near-optimal trees. Our experiments on sev- eral randomly generated problem instances and benchmarks confirm once again the supremacy of fidelity of Elmore delay over that of linear delay.
The Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), Newcastle, UK, April 5-8, 2008, Proceedings; 01/2008
[Show abstract][Hide abstract] ABSTRACT: Interconnect-driven optimization is an increasingly important step
in high-performance design. Algorithms for buffer insertion have been
successfully utilized to reduce delay in global interconnect paths;
however, existing techniques only optimize delay and timing slack, With
the continually increasing ratio of coupling capacitance to total
capacitance and the use of aggressive dynamic logic circuit families,
noise analysis and avoidance is becoming a major design bottleneck.
Hence, timing and noise must be simultaneously optimized to achieve
maximum performance. This paper presents comprehensive buffer insertion
techniques for noise and delay optimization. Three algorithms are
presented, the first for noise avoidance for single sink trees, the
second for avoidance for multiple sink trees, and the last for
simultaneous noise and delay optimization. We prove the optimality of
each algorithm (under various assumptions) and present other theoretical
results as well. We ran experiments on a high-performance microprocessor
design and show that our approach fixes all noise violations, Our
approach was separately verified by a detailed, simulation-based noise
analysis tool. Further, we show that optimizing delay alone cannot fix
all of the noise violations and that the performance penalty induced by
optimizing both delay and noise as opposed to only delay is less than 2%
[Show abstract][Hide abstract] ABSTRACT: Reduction of worst-case delay and delay uncertainty due to capacitive coupling is a still unsolved problem in physical design. We describe a routing only layout solution-swizzling-which reduces worst-case coupling delay for long parallel wires such as in wide on-chip global buses. We understand that swizzling is a folklore in structured-custom design community but we are the first to describe the method and analyze the potential benefits in literature. We give a general method for construction of good swizzling patterns. We also give empirically determined, optimal swizzling patterns for various technology nodes and typical repeater intervals. From our results, we see up to 31.5% reduction in worst-case delay and 34% reduction in delay uncertainty.
VLSI Design, 2004. Proceedings. 17th International Conference on; 02/2004
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