Conference Paper

Soft IP Protection: Watermarking HDL Codes

DOI: 10.1007/978-3-540-30114-1_16 Conference: Information Hiding, 6th International Workshop, IH 2004, Toronto, Canada, May 23-25, 2004, Revised Selected Papers
Source: DBLP


Intellectual property (IP) reuse based design is one of the most promising techniques to close the so-called design productivity gap. To facilitate better IP reuse, it is desirable to have IPs exchanged in the soft form such as hardware description language (HDL) source codes. However, soft IPs have higher protection requirements than hard IPs and most existing IP protection techniques are not applicable to soft IPs. In this paper, we describe the basic requirements, make the neces- sary assumptions, and propose several practical schemes for HDL code protection. We protect the HDL codes by hiding author's signature also called as watermarking, similar to the idea for hard IP and multimedia data pro- tection. But the new challenge is how to embed watermark into HDL source codes, which must be properly documented and synthesizable for reuse. We leverage the unique feature of Verilog HDL design to develop several watermarking techniques. These techniques can protect both new and existing Verilog designs. We watermark SCU-RTL & ISCAS bench- mark Verilog circuits, as well as a MP3 decoder. Both original and water- marked designs are implemented on ASICs & FPGAs. The results show that the proposed techniques survive the commercial synthesis tools and cause little design overhead in terms of area/resources, delay and power.

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    • "larger than the usually employed ones in the majority of the design examples available for other watermarking techniques [24] [26]. "
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    ABSTRACT: HDL-level design offers important advantages for the application of watermarking to IP cores, but its complexity also requires tools automating these watermarking algorithms. A new tool for signature distribution through combinational logic is proposed in this work. IPP@HDL, a previously proposed high-level watermarking technique, has been employed for evaluating the tool. IPP@HDL relies on spreading the bits of a digital signature at the HDL design level using combinational logic included within the original system. The development of this new tool for the signature distribution has not only extended and eased the applicability of this IPP technique, but it has also improved the signature hosting process itself. Three algorithms were studied in order to develop this automated tool. The selection of a cost function determines the best hosting solutions in terms of area and performance penalties on the IP core to protect. An 1D-DWT core and MD5 and SHA1 digital signatures were used in order to illustrate the benefits of the new tool and its optimization related to the extraction logic resources. Among the proposed algorithms, the alternative based on simulated annealing reduces the additional resources while maintaining an acceptable computation time and also saving designer effort and time.
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    • "It uses the run-time trace of a program and a particular program input (the secret key) to carry hidden information. An analogous approach was proposed to watermark HDL code for ASIC and FPGA design [16]. All these schemes aim at preventing software piracy, where hostile adversaries have strong incentives to remove the embedded watermark. "
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    ABSTRACT: Information hiding has been studied in many security applications such as authentication, copyright management and digital forensics. In this work, we introduce a novel approach based on lossless compression to generate space in compiled program binaries to enable information hiding without changing the instruction set architecture (ISA). We first analyze standard SPEC CPU2000 benchmark programs to demonstrate the feasibility of our proposed data hiding approach. That is, considerable space in the compiled program binaries could be saved by compression. Then we propose several techniques to hide a large amount of data in the operand fields of the program binaries with low computation and storage requirements. The data embedding is made reversible so the original instructions can be recovered to ensure the correct execution of the computer program. This data extraction process is performed by a light-weight on-chip hardware. Finally, we conduct a proof-of-the-concept FPGA prototyping to validate the data hiding technique and evaluate the hardware cost for the data extractor in terms of gate count, power consumption, and gate delay.
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    ABSTRACT: This paper argues for a new set of economic models for many-core computing. Current economic models for processors require a customer to estimate her average-case or worst-case computational requirements beforehand and then buy a processor/system that meets those needs. Physically changing the chip is the only way to transition between different peak computational capabilities, but it has associated cost and management overheads. Therefore, users tend to continue using the chip till a new system is bought. This causes computational resources on chips to often not match computational requirements of customers and/or applications, thereby resulting in processors that are often underutilized or over-utilized. Similarly, the one-to-one mapping between a chip and its available peak computational capability that the current economic models assume results in a mismatch between computational requirements of a user and the computational capabilities of a chip. This mismatch will only increase with increasing number of cores on the processor die. This paper presents four alternative economic models for many-core computing. The proposed models recognize that when a many-core chip is bought, the customer may often wish to pay for less number of cores than what is present on a chip. The models provide e xibility to the customer to change the available peak computational capability of the chip (or effective number of cores) during the lifetime of the chip. Two of the proposed models also allow the user to treat processing as a service by allowing the user to rent computational capability on the chip as well as pay only for the capability used. We discuss the hardware techniques that are required to support and enforce these economic models while honoring security and privacy concerns. We show that the required hardware support has a small area and power overhead.
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