Conference Paper

Soft IP Protection: Watermarking HDL Codes.

DOI: 10.1007/978-3-540-30114-1_16 Conference: Information Hiding, 6th International Workshop, IH 2004, Toronto, Canada, May 23-25, 2004, Revised Selected Papers
Source: DBLP

ABSTRACT Intellectual property (IP) reuse based design is one of the most promising techniques to close the so-called design productivity gap. To facilitate better IP reuse, it is desirable to have IPs exchanged in the soft form such as hardware description language (HDL) source codes. However, soft IPs have higher protection requirements than hard IPs and most existing IP protection techniques are not applicable to soft IPs. In this paper, we describe the basic requirements, make the neces- sary assumptions, and propose several practical schemes for HDL code protection. We protect the HDL codes by hiding author's signature also called as watermarking, similar to the idea for hard IP and multimedia data pro- tection. But the new challenge is how to embed watermark into HDL source codes, which must be properly documented and synthesizable for reuse. We leverage the unique feature of Verilog HDL design to develop several watermarking techniques. These techniques can protect both new and existing Verilog designs. We watermark SCU-RTL & ISCAS bench- mark Verilog circuits, as well as a MP3 decoder. Both original and water- marked designs are implemented on ASICs & FPGAs. The results show that the proposed techniques survive the commercial synthesis tools and cause little design overhead in terms of area/resources, delay and power.

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    ABSTRACT: Information hiding has been studied in many security applications such as authentication, copyright management and digital forensics. In this work, we introduce a novel approach based on lossless compression to generate space in compiled program binaries to enable information hiding without changing the instruction set architecture (ISA). We first analyze standard SPEC CPU2000 benchmark programs to demonstrate the feasibility of our proposed data hiding approach. That is, considerable space in the compiled program binaries could be saved by compression. Then we propose several techniques to hide a large amount of data in the operand fields of the program binaries with low computation and storage requirements. The data embedding is made reversible so the original instructions can be recovered to ensure the correct execution of the computer program. This data extraction process is performed by a light-weight on-chip hardware. Finally, we conduct a proof-of-the-concept FPGA prototyping to validate the data hiding technique and evaluate the hardware cost for the data extractor in terms of gate count, power consumption, and gate delay.
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    ABSTRACT: This paper presents significant improvements to our previous watermarking technique for Intellectual Property Protection (IPP) of IP cores. The technique relies on hosting the bits of a digital signature at the HDL design level using resources included within the original system. Thus, any attack trying to change or remove the digital signature will damage the design. The technique also includes a procedure for secure signature extraction requiring minimal modifications to the system. The new advances refer to increasing the applicability of this watermarking technique to any design, not only to those including look-ups, and the provision of an automatic tool for signature hosting purposes. Synthesis results show that the application of the proposed watermarking strategy results in negligible degradation of system performance and very low area penalties and that the use of the automated tool, in addition to easy the signature hosting, leads to reduced area penalties.
    Proceedings of SPIE - The International Society for Optical Engineering 05/2008; DOI:10.1117/12.777963 · 0.20 Impact Factor
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    ABSTRACT: The lack of absolute protection for the Intellectual Property Rights (IPR) of an IP provider has been a major hindrance of the IP core market for FPGAs. This work proposes a system that allows the IP provider to charge for the number of instances the core is used and protect against malicious over- deployment. The system is based on device-specific design encryption using secured device identification to ensure that the IP can only be deployed into explicitly identified and agreed upon devices. The system uses a combination of secret and public-key cryptographic functions devised for an uncomplicated trustable design exchange scenario. The public-key functions use modular squaring (Rabin Lock) instead of exponentiation to reduce the hardware complexity.


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