Conference Paper

A Novel Data-Path for Accelerating DSP Kernels.

University of Patras, Patras, Greece
DOI: 10.1007/978-3-540-27776-7_38 Conference: Computer Systems: Architectures, Modeling, and Simulation, Third and Fourth International Workshops, SAMOS 2003 and SAMOS 2004, Samos, Greece, July 21-23, 2003 and July 19-21, 2004, Proceedings
Source: DBLP


A high-performance data-path to implement DSP kernels is proposed in this paper. The data-path is based on a flexible, universal, and regular component that allows to optimally exploiting both inter-and intra-component chaining of operations. The introduced component is a combinational circuit with steering logic that allows in easily realizing any desirable complex hardware unit, called template; so that the data-path's performance benefits by the intra-component chaining of operations. Due to the component's flexible and universal structure, the Data Flow Graph is realized by a small number of such components. The small numbers of the used components coupled with a configurable interconnection network allow adopting direct inter-component connections and optimally exploiting any inter-component chaining possibility over to the existing template-based methods. Also, due to universal and flexible structure of the component, scheduling and binding are accomplished by simple, yet efficient, algorithms achieving minimum latency at the expense of an area penalty and a small overhead at the control circuit and clock period. Results on DSP benchmarks show an average latency reduction of 20%, when the proposed data-path is compared with a high-performance data-path.

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Available from: Dimitrios Soudris, Oct 09, 2015
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