Modeling, Simulation and Performance Evaluation for a CIOQ Switch Architecture.
ABSTRACT The intense growth experienced by the Internet on the past decade has motivated a considerable development in packet switching architectures. Several architectures have been proposed and implemented. Combined input-output queuing (CIOQ) is one of such successful architectures. In this paper, we present a proposal of modeling, simulation and performance evaluation for two CIOQ switch architectures developed by Santos and Motoyama. The main objective is to evaluate their performance and to compare main results. The performance evaluation covers blocking probability, mean and maximum queuing occupation for several switch dimensions and load intensities. Finally, we validated the proposal models and proved that Santos and Motoyama architectures are very efficient, with small blocking probabilities and queuing requirements.
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ABSTRACT: With the continuing increase in density of VLSI, limited buffer can be placed inside the crossbar and this combined input-crosspoint-queued (CICQ) switch structure decouples the inputs and outputs matching. In this paper, an analysis of the performance of Round-Robin scheduling algorithm for CICQ switch has been made proves that the Round-Robin algorithm can achieve 100% throughput under uniform traffic but not stable under non-uniform traffic. We propose the DRR algorithm, which can achieve 100% throughput under arbitrary traffic even buffered only one cell in crosspoints in CICQ switch DRR algorithm is feasible for fast hardware implementation and its time complexity is O(1)Modeling, Analysis, and Simulation of Computer and Telecommunication Systems, 2005. 13th IEEE International Symposium on; 10/2005
Conference Proceeding: Achieving 100% throughput in an input-queued switch[show abstract] [hide abstract]
ABSTRACT: It is well known that head-of-line (HOL) blocking limits the throughput of an input-queued switch with FIFO queues. Under certain conditions, the throughput can be shown to be limited to approximately 58%. It is also known that if non-FIFO queueing policies are used, the throughput can be increased. However it has not been previously shown that if a suitable queueing policy and scheduling algorithm are used then it is possible to achieve 100% throughput for all independent arrival processes. In this paper we prove this to be the case using a simple linear programming argument and quadratic Lyapunov function. In particular we assume that each input maintains a separate FIFO queue for each output and that the switch is scheduled using a maximum weight bipartite matching algorithmINFOCOM '96. Fifteenth Annual Joint Conference of the IEEE Computer Societies. Networking the Next Generation. Proceedings IEEE; 04/1996
Conference Proceeding: A QoS Provisioned CIOQ ATM Switch with m Internal Links.[show abstract] [hide abstract]
ABSTRACT: A QoS provisioned CIOQ ATM switch with m internal links is proposed in this paper. In the proposed switch the incoming cells at each input port are discriminated into service classes. For each service class, at each input port, a single buffer is provided whereas each output port needs m buffers, where m is the number of internal links (or channels) that connect each input port to each output port. The proposed switch uses physical internal links instead of time division, thus no speedup is required. The results of simulation of proposed switch using simple priority schedulers show that for m≥3 the number of cell waiting at input queue is small, less than 0,1 cells in average, independent of service classes. The proposed switch has also the feature that facilitates the choice of scheduler in order to satisfy the QoS of each class of service.Telecommunications and Networking - ICT 2004, 11th International Conference on Telecommunications, Fortaleza, Brazil, August 1-6, 2004, Proceedings; 01/2004