Rijndael FPGA Implementations Utilising Look-Up Tables.
ABSTRACT This paper presents single-chip FPGA Rijndael algorithm implementations of the Advanced Encryption Standard (AES) algorithm, Rijndael. In particular, the designs utilise look-up tables to implement the entire Rijndael Round function. A comparison is provided between these designs and similar existing implementations. Hardware implementations of encryption algorithms prove much faster than equivalent software implementations and since there is a need to perform encryption on data in real time, speed is very important. In particular, Field Programmable Gate Arrays (FPGAs) are well suited to encryption implementations due to their flexibility and an architecture, which can be exploited to accommodate typical encryption transformations. In this paper, a Look-Up Table (LUT) methodology is introduced where complex and slow operations are replaced by simple LUTs. A LUT-based fully pipelined Rijndael implementation is described which has a pre-placement performance of 12 Gbits/sec, which is a factor 1.2 times faster than an alternative design in which look-up tables are utilised to implement only one of the Round function transformations, and 6 times faster than other previous single-chip implementations. Iterative Rijndael implementations based on the Look-Up-Table design approach are also discussed and prove faster than typical iterative implementations.
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ABSTRACT: Summary In this paper, we present a novel Field Programmable Gate Array (FPGA) implementation of advanced encryption standard (AES- 128) algorithm based on the design of high performance S-Box built using reduced residue of prime numbers. The objective is to present an efficient hardware realization of AES-128 using very high speed integrated circuit hardware description language (VHDL). The novel S-Box look up table (LUT) entries forms a set of reduced residue of prime number, which forms a mathematical field. The S-Box with reduced residue of prime number adds more confusion to the entire process of AES algorithm and makes it more complex and provides further resistance against attacks. The target hardware used in this paper is state-of-the-art Virtex-5 XC5VLX50 FPGA from Xilinx. The proposed design achieves a throughput of 3.09 Gbps using only 1745 slices.International Journal of Computer Science and Network Security. 09/2009; 9(9):305-309.
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ABSTRACT: The rapid development, advancement, and growing use of satellite imagery and information technologies have made the security of data storage and transmission essential to prevent unlawful, unofficial, unauthorized, and illegal use/access. This paper proposes a secure satellite image encryption technique based on chaotic and Advanced Encryption Standard (AES) techniques to protect critical and confidential satellite imagery. Arnold’s cat map is used to shuffle the pixel values. A chaotic Henon map is used to generate a random sequence for the AES algorithm, and the shuffled-image is encrypted using the AES algorithm. The security and performance is acceptable to deal with high resolution and multi-spectral satellite imagery. The experimental results are shown, along with those for some traditional encryption techniques, for a comparison and evaluation. Detailed experimental results are also given of the security, statistical, and performance analyses of the complete implementation of the new proposed solution. The proposed technique presents numerous interesting and attractive features, including a high level of security, sufficiently large key-space with improved key sensitivity, pixel distributing uniformity, and acceptable speed.Telecommunication Systems 01/2013; · 1.03 Impact Factor