Energy Optimization of Multiprocessor Systems on Chip by Voltage Selection.
IEEE Trans. VLSI Syst 01/2007; 15:262-275. pp.262-275
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ABSTRACT: Large-scale integration with deep sub-micron technologies has led to high power densities and high chip working temperatures. At the same time, leakage energy has become the dominant energy consumption source of circuits due to reduced threshold voltages. Given the close interdependence between temperature and leakage current, temperature has become a major issue to be considered for power-aware system level design techniques. In this paper, we address the issue of leakage energy optimization through temperature aware idle time distribution (ITD). We first propose an offline ITD technique to optimize leakage energy consumption, where only static idle time is distributed. To account for the dynamic slack, we then propose an online ITD technique where both static and dynamic idle time are considered. To improve the efficiency of our ITD techniques, we also propose an analytical temperature analysis approach which is accurate and, yet, sufficiently fast to be used inside the energy optimization loop.IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 1.22 Impact Factor
Article: Energy Optimization for Many-Core Platforms: Communication and PVT Aware Voltage-Island Formation and Voltage Selection Algorithm.IEEE Trans. on CAD of Integrated Circuits and Systems. 01/2010; 29:816-829.
Conference Proceeding: Temperature-aware idle time distribution for energy optimization with dynamic voltage scaling.Design, Automation and Test in Europe, DATE 2010, Dresden, Germany, March 8-12, 2010; 01/2010
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