A Low-Jitter Open-Loop All-Digital Clock Generator With Two-Cycle Lock-Time

Electr. & Electron. Eng. Dept., Korea Univ., Seoul, South Korea
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (Impact Factor: 1.36). 10/2009; 17(10):1461-1469. DOI: 10.1109/TVLSI.2008.2004591
Source: DBLP


A portable clock generator, which solves the duty ratio and jitter problems of the input clock, has been developed. In the proposed clock generator, the complementary delay line generates a series of multiphase clocks. The 0-to-1 transition detector finds the 2 pi phase delayed position among the multiphase clocks produced by the complementary delay line, and then, the select signal generator chooses the proper path to generate the delayed output clock. As a result, the proposed open-loop and full-digital architecture achieves a fast lock time of two clock cycles. Also, it is a simple, robust and portable IP and consumes only 17 mW at an input clock frequency of 1.6 GHz. In addition, a complementary delay line is implemented to achieve high phase resolution over a wide frequency range. The proposed clock generator is implemented in a 0.18-mum CMOS process and, occupies an active area of 170 mum times 120 mum. Also, it operates at various input frequencies ranging from 800 MHz to 1.6 GHz.

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    • "Digital Object Identifier 10.1109/TVLSI.2011.2106170 been demonstrated in [5] and analog and digital solutions to the false detection problem are developed in [1]. DLL-based clock generation with frequency scaling is presented in [3]. "
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    ABSTRACT: A digital delay-locked loop (DLL) suitable for generation of multiphase clocks in applications such as time-interleaved and pipelined analog-to-digital converters (ADCs) locks in a very wide (40×) frequency range. The DLL provides 12 uniformly delayed phases, free of false harmonic locking. A two-stage digital split-control loop is implemented: a fast-locking coarse acquisition is achieved in four cycles using binary search; a fine linear loop achieves low jitter (9 ps rms @ 600 MHz) and tracks process, voltage, and temperature (PVT) variations. The false harmonic locking detector, the frequency range and the jitter performance among other design considerations are analyzed in detail. The DLL consumes 20 mW and occupies a 470 μm × 800 μm in 0.13 μm CMOS.
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems 04/2012; 20(3-20):564 - 568. DOI:10.1109/TVLSI.2011.2106170 · 1.36 Impact Factor
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    ABSTRACT: An all-digital fast-lock synchronous multi-phase clock generator is presented. By using a time-to-digital converter for fast-lock operation and delay measurement, the proposed multi-phase clock generator generates four-phase clocks and synchronizes the reference clock with the output clock within 45 cycles. Furthermore, the clock generator uses a fine binary scheme and de-skewing circuit for fine delay measurement and compensation. The proposed clock generator was designed in a 0.18 mum CMOS technology. It operates over a wide frequency range from 400 MHz to 1.22 GHz and consumes 34 mW at 1.22 GHz.
    International Symposium on Circuits and Systems (ISCAS 2009), 24-17 May 2009, Taipei, Taiwan; 01/2009
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