A Low-Jitter Open-Loop All-Digital Clock Generator With Two-Cycle Lock-Time.

Electr. & Electron. Eng. Dept., Korea Univ., Seoul, South Korea
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (Impact Factor: 1.22). 01/2009; 17:1461-1469. DOI: 10.1109/TVLSI.2008.2004591
Source: DBLP

ABSTRACT A portable clock generator, which solves the duty ratio and jitter problems of the input clock, has been developed. In the proposed clock generator, the complementary delay line generates a series of multiphase clocks. The 0-to-1 transition detector finds the 2 pi phase delayed position among the multiphase clocks produced by the complementary delay line, and then, the select signal generator chooses the proper path to generate the delayed output clock. As a result, the proposed open-loop and full-digital architecture achieves a fast lock time of two clock cycles. Also, it is a simple, robust and portable IP and consumes only 17 mW at an input clock frequency of 1.6 GHz. In addition, a complementary delay line is implemented to achieve high phase resolution over a wide frequency range. The proposed clock generator is implemented in a 0.18-mum CMOS process and, occupies an active area of 170 mum times 120 mum. Also, it operates at various input frequencies ranging from 800 MHz to 1.6 GHz.

  • [Show abstract] [Hide abstract]
    ABSTRACT: This paper proposes an all-digital clock synchronization buffer (CSB) with one-cycle dynamic synchronization. The CSB synchronizes the input and output clocks in three clock cycles but maintains one cycle at fastest operating frequency. The CSB achieves one-cycle dynamic locking and synchronizes the dynamic frequencies with a modified structure. The CSB compensates for dynamic phase error with a modified fine-tuned circuit. The chip is fabricated using a 130-nm standard CMOS process. Its operating frequency range is between 300 MHz and 800 MHz. The power consumption and RMS jitter are 2.4 mW and 2.25 ps at 800 MHz, respectively. The active area of this chip is 0.015 mm2.
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems 10/2012; 20(10):1818-1827. · 1.22 Impact Factor
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: A digital delay-locked loop (DLL) suitable for generation of multiphase clocks in applications such as time-interleaved and pipelined analog-to-digital converters (ADCs) locks in a very wide (40×) frequency range. The DLL provides 12 uniformly delayed phases, free of false harmonic locking. A two-stage digital split-control loop is implemented: a fast-locking coarse acquisition is achieved in four cycles using binary search; a fine linear loop achieves low jitter (9 ps rms @ 600 MHz) and tracks process, voltage, and temperature (PVT) variations. The false harmonic locking detector, the frequency range and the jitter performance among other design considerations are analyzed in detail. The DLL consumes 20 mW and occupies a 470 μm × 800 μm in 0.13 μm CMOS.
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems 04/2012; · 1.22 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: This brief presents a continuous-time impulse radio ultrawideband transmitter. The transmitter is a part of a high-precision ranging single-chip transceiver that measures the time-of-flight symbol propagation. The clock burst generator in the transmitter will initiate symbol transmission in continuous time unbounded by any clock signal while maintaining an accurate chip rate during symbol transmission. Using a calibration circuit, the clock period can be programmed precisely to compensate for device mismatch. The transmitter is fabricated in Taiwan Semiconductor Manufacturing Company 90-nm CMOS technology and occupies an area of 0.123 mm2. The programmable clock range is from 12.65 to 111 MHz, and the measured rms jitter is 3.26 ps at 50 MHz. The entire transmitter has a power consumption of 1.41 mW at the data rate of 2 Mbit/s.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 01/2013; 60(11):721-725. · 1.33 Impact Factor