A Low-Jitter Open-Loop All-Digital Clock Generator With Two-Cycle Lock-Time.

Electr. & Electron. Eng. Dept., Korea Univ., Seoul, South Korea
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (Impact Factor: 1.14). 10/2009; 17:1461-1469. DOI: 10.1109/TVLSI.2008.2004591
Source: DBLP

ABSTRACT A portable clock generator, which solves the duty ratio and jitter problems of the input clock, has been developed. In the proposed clock generator, the complementary delay line generates a series of multiphase clocks. The 0-to-1 transition detector finds the 2 pi phase delayed position among the multiphase clocks produced by the complementary delay line, and then, the select signal generator chooses the proper path to generate the delayed output clock. As a result, the proposed open-loop and full-digital architecture achieves a fast lock time of two clock cycles. Also, it is a simple, robust and portable IP and consumes only 17 mW at an input clock frequency of 1.6 GHz. In addition, a complementary delay line is implemented to achieve high phase resolution over a wide frequency range. The proposed clock generator is implemented in a 0.18-mum CMOS process and, occupies an active area of 170 mum times 120 mum. Also, it operates at various input frequencies ranging from 800 MHz to 1.6 GHz.

  • [Show abstract] [Hide abstract]
    ABSTRACT: The adiabatic dynamic CMOS logic (ADCL) has been studied to reduce the power dissipation in conventional CMOS logic. The clock signal of logic circuits should be synchronized with the AC power source to maintain adiabatic charging/discharging with low power for the ADCL. In this paper, an ultra low-power synchronizer using ADCL buffer is proposed. The ADCL buffer has been designed using features of automatic synchronization between AC signal and output of gate stage. Power consumptions of the proposed ADCL synchronizer are found to be 99.4 nW at best case and 109.8 nW at worst case, when AC signal and clock frequencies are 110 MHz and 10 MHz, respectively.
    IEICE Electronics Express 01/2012; 9(20):1576-1585. DOI:10.1587/elex.9.1576 · 0.39 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: This work proposes a low supply voltage synchronous mirror delay (SMD) circuit with quadrature phase output in intra-chip. In some application-specific integrated chips (ASICs) or silicon intellectual properties (IPs) might enter hibernation mode to conserve energy. The long locking time induces a large standby current, which results in greater power consumption. Furthermore, for some specific applications, the circuits need to operate in a low supply voltage environment. In some communication systems, they even need to have I/Q clock signals. Therefore, this is often led to a synchronous circuit with extra functional capabilities. The proposed SMD with the quadrature delay path can operate in the low supply voltage environment by using the low-voltage techniques. The chip is implemented by TSMC CMOS 1P/9M 90 nm technology with a low supply voltage, 0.5 V. The operation range is from 220 MHz to 570 MHz, and the power consumption is 1.95 mW at 570 MHz. The peak-to-peak jitter and RMS jitter of internal clock are 31.78 ps and 3.99 ps at 570 MHz, respectively. The peak-to-peak jitter and RMS jitter of quadrature internal clock are 34.67 ps and 4.48 ps at 570 MHz, respectively. The core area is 188 × 171 um2.
    2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS); 04/2014
  • [Show abstract] [Hide abstract]
    ABSTRACT: Proposed is a dynamic frequency tracking and phase error compensation clock de-skew buffer (CDSB) to reduce the clock skew between the input and output clocks of a chip. The proposed CDSB tracks the dynamic frequency in two clock cycles. Also, the CDSB utilises a fine tune circuit which is based on a cyclic rotation algorithm to compensate for the dynamic phase error. Measured results show that the operating frequencies of the CDSB are from 200 to 450 MHz. Also, the CDSB tracks the dynamic frequency in two clock cycles. The power consumption, RMS jitter, and peak-to-peak jitter of the CDSB are 9.71 mW, 2.7 ps, and 31.3 ps at 450 MHz.
    Electronics Letters 01/2011; 46(25-46):1653 - 1655. DOI:10.1049/el.2010.2872 · 1.07 Impact Factor