A Low-Jitter Open-Loop All-Digital Clock Generator With Two-Cycle Lock-Time.

Electr. & Electron. Eng. Dept., Korea Univ., Seoul, South Korea
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (Impact Factor: 1.22). 01/2009; 17:1461-1469. DOI: 10.1109/TVLSI.2008.2004591
Source: DBLP

ABSTRACT A portable clock generator, which solves the duty ratio and jitter problems of the input clock, has been developed. In the proposed clock generator, the complementary delay line generates a series of multiphase clocks. The 0-to-1 transition detector finds the 2 pi phase delayed position among the multiphase clocks produced by the complementary delay line, and then, the select signal generator chooses the proper path to generate the delayed output clock. As a result, the proposed open-loop and full-digital architecture achieves a fast lock time of two clock cycles. Also, it is a simple, robust and portable IP and consumes only 17 mW at an input clock frequency of 1.6 GHz. In addition, a complementary delay line is implemented to achieve high phase resolution over a wide frequency range. The proposed clock generator is implemented in a 0.18-mum CMOS process and, occupies an active area of 170 mum times 120 mum. Also, it operates at various input frequencies ranging from 800 MHz to 1.6 GHz.

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