A Novel Soft Error Detection and Correction Circuit for Embedded Reconfigurable Systems.
ABSTRACT As the size of integrated circuits has reached the nanoscale, embedded memories are more sensitive to single-event upsets (SEUs) or double-event upsets (DEUs), due to their low threshold voltage. In particular, reconfigurable systems, con- taining a large number of configuration memories to implement customer circuits, are more likely to suffer from soft errors caused by SEUs and DEUs. In this letter, we develop a Hamming code based error detection and correction (EDAC) circuit that can protect the configuration memory of a reconfigurable device from SEUs. Evaluation reveals that compared to the conventional triple modular redundancy (TMR) protected field-programmable gate array (FPGA) tile, the proposed EDAC protected FPGA tile shows about 2.3 times better dependability on the influence of DEUs. Moreover, as the FPGA array size increases, the dependability advantage of EDAC increases exponentially. The main drawback of EDAC is that it has about 1.6 times greater area overhead than TMR.
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ABSTRACT: Despite widespread use of SRAM-based reconfigurable devices (SRDs) in mainstream applications, their usage has been very limited in enterprise and safety-critical applications due to SRAM susceptibility to soft errors. Previous mitigation techniques to protect SRDs impose significant area and power overheads. Additionally, they suffer from susceptibility of configuration bits to multiple bit upsets (MBUs). In this paper, we present a highly available fault-tolerant architecture to protect SRD-based designs against MBUs in both configuration and user bits. In the proposed architecture, the entire design is duplicated with respect to the relative locations of logic blocks within the SRD and the main and replica flip-flops (FFs) are compared at each clock cycle to detect any possible mismatch. In addition, the unused FFs available throughout SRDs are employed as history FFs to save the latest correct state of the system. Upon detection of any mismatch between the main and replica FFs, the system is able to roll back to the latest correct state stored in the history FFs. The simulation results extracted using fault injection experiments demonstrate that the proposed architecture provides both higher reliability and availability, as compared with the traditional triple modular redundancy techniques, while offering less area and power overheads.IEEE Transactions on Device and Materials Reliability 03/2013; 13(1):203-212. · 1.54 Impact Factor
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ABSTRACT: Soft errors in the configuration memory of SRAM-based FPGAs cause significant and remanent application disturbances. Typical mitigation techniques induce large overheads in terms of resource usage and power consumption. We propose a new approach achieving efficient trade-offs between robustness and overheads, applied to the internal architecture of commercial AT40K devices.Circuits and Systems (LASCAS), 2012 IEEE Third Latin American Symposium on; 01/2012