A Novel Soft Error Detection and Correction Circuit for Embedded Reconfigurable Systems.
ABSTRACT As the size of integrated circuits has reached the nanoscale, embedded memories are more sensitive to single-event upsets (SEUs) or double-event upsets (DEUs), due to their low threshold voltage. In particular, reconfigurable systems, con- taining a large number of configuration memories to implement customer circuits, are more likely to suffer from soft errors caused by SEUs and DEUs. In this letter, we develop a Hamming code based error detection and correction (EDAC) circuit that can protect the configuration memory of a reconfigurable device from SEUs. Evaluation reveals that compared to the conventional triple modular redundancy (TMR) protected field-programmable gate array (FPGA) tile, the proposed EDAC protected FPGA tile shows about 2.3 times better dependability on the influence of DEUs. Moreover, as the FPGA array size increases, the dependability advantage of EDAC increases exponentially. The main drawback of EDAC is that it has about 1.6 times greater area overhead than TMR.
Conference Proceeding: A robust reconfigurable logic device based on less configuration memory logic cell[show abstract] [hide abstract]
ABSTRACT: As the size of integrated circuit has reached the nanoscale, embedded memories are more sensitive to single event upset (SEU), because of their low threshold voltage. In particular field-programmable gate arrays (FPGAs), which contain large amounts of configuration memories to implement customer circuits, are more likely to suffer from soft errors caused by SEU. In this research, we first develop a Hamming code based error detect and correct (EDC) circuit that can prevent the configuration memory of a reconfigurable device from SEU. We then propose a novel reconfigurable logic element, namely COGRE, which will use much less configuration memory than the conventional FPGA 4-, 5- or 6-LUTs (lookup tables). Evaluation revealed that compared to the 6-LUT FPGAs with triple modular redundancy (TMR) configuration memory blocks, the 5- and 6-input proposed architecture save about 75.44 and 74.29% memories on average, respectively. And the dependability of the proposed architectures is about 6.8 to 10 times better than the LUTs with a tile level TMR structure on average. Moreover, with the consideration of the on the fly scrubbing advantage of the EDC, SEUs cannot be accumulated, so a much higher dependability can be achieved.Field-Programmable Technology (FPT), 2010 International Conference on; 01/2011
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ABSTRACT: A concurrent error detection (CED) scheme for combinational logic blocks implemented with embedded memory blocks (EMBs) available in today's FPGAs is proposed. The scheme guarantees the detection of each permanent or transient fault resulting in a single-bit error at the input or output of any component of the circuit. Extensions of the basic scheme aimed at increasing the set of target faults are also presented. For the examined benchmark circuits, an average overhead associated with the proposed CED scheme is 24.7%, whereas for the earlier presented CED techniques applicable to conventional gate-based designs, an average overhead for the same circuits is in the range of 60%. The proposed technique offers also lower speed degradation and lower extra power consumption than the techniques intended for conventional gate-based designs.Design and Diagnostics of Electronic Circuits and Systems, 2008. DDECS 2008. 11th IEEE Workshop on; 05/2008
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ABSTRACT: A comparison of two scrubbing mitigation schemes for Xilinx field programmable gate array devices is presented. The design of the scrubbers is briefly discussed along with an examination of mitigation limitations. Heavy ion data are then presented and analyzed.IEEE Transactions on Nuclear Science 09/2008; · 1.22 Impact Factor