Leakage Minimization of Digital Circuits Using Gate Sizing in the Presence of Process Variations.
ABSTRACT This paper presents a novel gate-sizing methodology to minimize the leakage power in the presence of process variations. The method is based on modeling the statistics of leakage and delay as posynomials functions to formulate a geometric-programming problem. The existing statistical leakage model is extended to include the variations in gate sizes, as well as systematic variations. Using a simplified delay model, we propose an efficient method to evaluate the alpha-percentile of path delays without enumerating the paths in a circuit. The complexity of evaluating the objective function of the optimization problem is O(|N|2) and that of evaluating the delay constraints is O(|N| + |E|) for a circuit with |N| gates and |E| wires. The optimization problem is then solved using a convex optimization algorithm that gives an exact solution. The statistical optimization methodology is shown to provide as much as 15% reduction in the mean leakage power as compared to traditional worst case gate sizing with the same delay constraints.
Conference Paper: Statistical leakage estimation of bounds on nanometric CMOS circuits[Show abstract] [Hide abstract]
ABSTRACT: In this work is presented one method of statistical leakage estimation of bounds in CMOS circuits based on the characterization of standard CMOS cell libraries. The leakage estimation takes in account the correlations (rho) of cells structure, input patters and variations on principal process parameters. Also it was considered the presence of Intra-Die process variations for spatial correlations beta = 1 and 0 larr beta rarr 1. For the complete ISCAS85 Benchmark under study the mu and sigma2 absolute errors varies between 0.0048 to 0.1278 & 0.0301 to 0.3801 for lower bound and 0.0306 to 0.1247 & 0.0411 to 0.2016 for upper bound.Design & Technology of Integrated Systems in Nanoscal Era, 2009. DTIS '09. 4th International Conference on; 01/2009
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ABSTRACT: SUMMARY Leakage current is an important qualitative metric of LSI (Large Scale Integrated circuit). In this paper, we focus on reduction of leakage current variation under the process variation. Firstly, we derive a set of quadratic equations to evaluate delay and leakage current under the process variation. Using these equations, we discuss the cases of varying leakage current without degrading delay distribution and propose a proce- dure to reduce the leakage current variations. From the experiments, we show the proposed method effectively reduces the leakage current varia- tion up to 50% at 90 percentile point of the distribution compared with the conventional design approach.
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ABSTRACT: Dynamic CMOS circuits are significantly used in high-performance very large-scale integrated (VLSI) systems. However, they suffer from limitations such as noise tolerance, charge leakage, and power consumption. With the escalating impact of process variations on design performance, aggressive technology scaling, noise in dynamic CMOS circuit has become an imperative design challenge. The design performance of dynamic circuits has to be first improved for reliable operation of VLSI systems. Alongside, this impact of process variation is worse in circuits with multiple timing paths such as those used in microprocessors. In this paper, these problems of process variations, timing, noise tolerance, and power are investigated together for performance optimization. We propose a process variation-aware load-balance of multiple paths transistor sizing algorithm to: 1) improve worst-case delay, delay uncertainty, and sensitivity due to process variations in dynamic CMOS circuits, and 2) optimize dynamic CMOS circuits with MOSFET-based keepers to improve the noise tolerance. Implemented using 90-nm CMOS process, the proposed algorithm has demonstrated an average improvement in worst-case delay by 34%, delay uncertainty by 40.3%, delay sensitivity by 25.1%, and noise margins by 19.4% when compared to their initial performances.IEEE Transactions on Semiconductor Manufacturing 01/2012; 25(2):255-265. · 0.86 Impact Factor