Leakage Minimization of Digital Circuits Using Gate Sizing in the Presence of Process Variations.
ABSTRACT This paper presents a novel gate-sizing methodology to minimize the leakage power in the presence of process variations. The method is based on modeling the statistics of leakage and delay as posynomials functions to formulate a geometric-programming problem. The existing statistical leakage model is extended to include the variations in gate sizes, as well as systematic variations. Using a simplified delay model, we propose an efficient method to evaluate the alpha-percentile of path delays without enumerating the paths in a circuit. The complexity of evaluating the objective function of the optimization problem is O(|N|2) and that of evaluating the delay constraints is O(|N| + |E|) for a circuit with |N| gates and |E| wires. The optimization problem is then solved using a convex optimization algorithm that gives an exact solution. The statistical optimization methodology is shown to provide as much as 15% reduction in the mean leakage power as compared to traditional worst case gate sizing with the same delay constraints.
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ABSTRACT: We present a new approach for estimation and optimization of the average stand-by power dissipation in large MOS digital circuits. To overcome the complexity of state dependence in average leakage estimation, we introduce the concept of “dominant leakage states” and use state probabilities. Our method achieves speed-ups of 3 to 4 orders of magnitude over exhaustive SPICE simulations while maintaining accuracies within 9% of SPICE. This accurate estimation is used in a new sensitivity-based leakage and performance optimization approach for circuits using dual Vt processes. In tests on a variety of industrial circuits, this approach was able to obtain 81-100% of the performance achievable with all low Vt transistors, but with 1/3 to 1/6 the stand-by currentDesign Automation Conference, 1999. Proceedings. 36th; 01/1999
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ABSTRACT: Variability in digital integrated circuits makes timing ver- ication an extremely challenging task. In this paper, a canonical rst order delay model is proposed that takes into account both correlated and independent randomness. A novel linear-time block-based statistical timing algorithm is employed to propagate timing quantities like arrival times and required arrival times through the timing graph in this canonical form. At the end of the statistical timing, the sensitivities of all timing quantities to each of the sources of variation are available. Excessive sensitivities can then be targeted by manual or automatic optimization methods to improve the robustness of the design. The statistical timing analysis is incremental, and is therefore suitable for use in the inner loop of physical synthesis or other optimization programs. The second novel contribution of this paper is the computation of local and global criticality probabilities. For a very small cost in CPU time, the probability of each edge or node of the timing graph being critical is computed. These criticality probabilities provide additional useful diag- nostics to synthesis, optimization, test generation and path enumeration programs. Numerical results are presented on industrial ASIC chips with over two million logic gates.IEEE Trans. on CAD of Integrated Circuits and Systems. 01/2006; 25:2170-2180.
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ABSTRACT: this paper.Given the MOS circuit topology, the delay can be controlled byvarying the sizesof transistors in the circuit. Here, the size of a transistor is measured in terms of its channelwidth, since the channel lengths in a digital circuit are generally uniform. Roughly speaking,the sizes of certain transistors can be increased to reduce the circuit delay at the expense ofadditional chip areaIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 01/1993; 12:1621-1634. · 1.09 Impact Factor