Leakage Minimization of Digital Circuits Using Gate Sizing in the Presence of Process Variations.

Synopsys, Inc., Mountain View
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (Impact Factor: 1.2). 03/2008; 27:445-455. DOI: 10.1109/TCAD.2008.916341
Source: DBLP

ABSTRACT This paper presents a novel gate-sizing methodology to minimize the leakage power in the presence of process variations. The method is based on modeling the statistics of leakage and delay as posynomials functions to formulate a geometric-programming problem. The existing statistical leakage model is extended to include the variations in gate sizes, as well as systematic variations. Using a simplified delay model, we propose an efficient method to evaluate the alpha-percentile of path delays without enumerating the paths in a circuit. The complexity of evaluating the objective function of the optimization problem is O(|N|2) and that of evaluating the delay constraints is O(|N| + |E|) for a circuit with |N| gates and |E| wires. The optimization problem is then solved using a convex optimization algorithm that gives an exact solution. The statistical optimization methodology is shown to provide as much as 15% reduction in the mean leakage power as compared to traditional worst case gate sizing with the same delay constraints.

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