New Montgomery-based Semi-systolic Multiplier for Even-type GNB of GF(2^m).
ABSTRACT Efficient finite field multiplication is crucial for implementing public key cryptosystem. Based on new Gaussian normal basis Montgomery (GNBM) representation, this paper presents a semi-systolic even-type GNBM multiplier. Compared with the only existing semi-systolic even-type GNB multiplier, the proposed multiplier saves about 57% space complexity and 50% time complexity. Index Terms—Finite field multiplication, Gaussian normal basis, elliptic curve cryptosystem, Montgomery, systolic architecture.
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ABSTRACT: Using the self duality of an optimal normal basis (ONB) of type II, we present a bit parallel systolic multiplier over GF(2<sup>m</sup>), which has a low hardware complexity and a low latency. We show that our multiplier has a latency m+1 and the basic cell of our circuit design needs 5 latches (flip-flops). On the other hand, most of other multipliers of the same type have latency 3m and the basic cell of each multiplier needs 7 latches. Comparing the gates areas in each basic cell, we find that the hardware complexity of our multiplier is 25 percent reduced from the multipliers with 7 latches.Computer Arithmetic, 2003. Proceedings. 16th IEEE Symposium on; 07/2003
Conference Proceeding: Improved VLSI designs for multiplication and inversion in GF(2M) over normal bases[show abstract] [hide abstract]
ABSTRACT: Finite field arithmetic circuits are a core part for implementing some cryptographic systems and Reed-Solomon codes. In this paper, improved VLSI designs for computing multiplication and inverse in GF(2 <sup>m</sup>) over normal bases are presented. The improvements over the previous publications for the Massey-Omura multiplier include both circuit and architecture (or logic) levels. At circuit level, the improved design reduces the area and power consumption, and is faster than the previous design. At architecture level, the new design reduces logic complexity and is more regular, which, in turn, allows static CMOS design and reduces power dissipation. The latency of the inversion method is reduced with parallelism exploration at no cost in hardware. Therefore, the work presented in this paper can provide better VLSI designs in terms of performance and power consumptionASIC/SOC Conference, 2000. Proceedings. 13th Annual IEEE International; 02/2000
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ABSTRACT: Fault-based cryptanalysis has been developed to effectively break both private-key and public-key cryptosystems, making robust finite field multiplication a very important research topic in recent years. However, no robust normal basis multiplier has been proposed in the literature. Therefore, this investigation presents a semisystolic Gaussian normal basis multiplier. Based on the proposed Gaussian normal basis multiplier, both concurrent error detection and correction capabilities can be easily achieved using time redundancy technology with no hardware modification.IEEE Transactions on Computers 12/2008; 58:851-857. · 1.38 Impact Factor