Power-aware SoC test planning for effective utilization of port-scalable testers.

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Power-Aware SoC Test Planning for Effective
Utilization of Port-Scalable Testers
ANUJA SEHGAL, SUDARSHAN BAHUKUDUMBI, and
KRISHNENDU CHAKRABARTY
Duke University
Manysystem-on-chip(SoC)integratedcircuitscontainembeddedcoreswithdifferentscanfrequen-
cies. To better meet the test requirements for such heterogeneous SoCs, leading tester companies
have recently introduced port-scalable testers, which can simultaneously drive groups of channels
at different data rates. However, the number of tester channels available for scan testing is limited;
therefore, a higher shift frequency can increase the test time for a core if the resulting test access
architecture reduces the bit-width used to access it. We present a scalable test planning technique
that exploits port scalability of testers to reduce SoC test time. We compare the proposed heuristic
optimization method to two baseline methods based on prior works that use a single scan data
rate for all embedded cores. We also propose a power-aware test planning technique to effectively
utilize port-scalable testers under constraints of test power consumption. Experimental results are
presented for power-aware test scheduling to illustrate the impact of power constraints on overall
test time.
Categories and Subject Descriptors: B.7.3 [Integrated Circuits]: Reliability and Testing
General Terms: Algorithms, Design, Reliability
Additional Key Words and Phrases: SoC test, port-scalable testers, test access architecture, integer
linear programming
ACM Reference Format:
Sehgal, A., Bahukudumbi, S., and Chakrabarty, K. 2008. Power-aware SoC test planning for
effective utilization of port-scalable testers. ACM Trans. Des. Autom. Electron. Syst. 13, 3,
Article 53 (July 2008), 19 pages, DOI = 10.1145/1367045.1367062 http://doi.acm.org/10.1145/
1367045.1367062
A. Sehgal is with the NVIDIA Corporation and worked on this article as a graduate student at
Duke University, Durham, NC 27708.
ThisresearchwassupportedinpartbytheNationalScienceFoundationundergrantCCR-0204077.
A shorter version of this article was published in Proceedings of the IEEE International Conference
on Computer-Aided Design, 2005, pp. 88–93.
Authors’ addresses: A. Sehgal, NVIDIA Corporation, 2701 San Tomas Expressway, Santa Clara,
CA 95050; email: asehgal@nvidia.com; S. Bahukudumbi, K. Chakrabarty, Department of Electrical
andComputerEngineering,DukeUniversity,Durham,NC27708;email:{spb,krish}@ee.duke.edu.
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10.1145/1367045.1367062

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1. INTRODUCTION
Recent advances in technology have led to a tremendous increase in the com-
plexity of system-on-chip (SoC) integrated circuits. Today’s heterogeneous SoCs
consist of embedded cores that not only operate in multiple clock domains [Goel
et al. 2004; Lin and Thompson 2003; Schmid and Knablein 1999], but also (due
to differences in performance levels, design styles, and scan insertion methods)
differ in their maximum scan clock frequencies [Vranken et al. 2003]. The dif-
ference in scan clock frequencies between embedded cores can also arise due to
the integration of various cores derived from different, older-generation SoCs
into a single, current-generation SoC [Chickermane et al. 2001]. The test time
for such SoCs can be reduced by testing the embedded cores at data-transfer
rates that match their maximum scan frequencies.
To test embedded cores at different scan frequencies, the test data needs to
be simultaneously transported at multiple data rates on the tester channels. In
order to meet this requirement, automatic test equipment (ATE) vendors have
introduced a new class of testers that can simultaneously drive tester channels
at different data rates [Dorsch et al. 2002]. Examples of such ATEs include the
Agilent 93000 series [Agilent Technologies 2002; Agilent 93000 2008] and the
Tiger system from Teradyne [Teradyne Technologies 2008], which are based on
port scalability and test processor-per-pin architecture. Port scalability allows
every port of a tester to be configured at a desired data rate, where each port
typically consists of multiple channels.
Modular testing of embedded cores offers a promising test solution for SoCs
[Goel et al. 2004; Zorian et al. 1999]. It also lends itself well to the scenario
of SoC testing using multiple scan data rates. It involves the isolation of an
embedded core from surrounding logic using a test wrapper, and the design of a
testaccessmechanism(TAM)todelivertestdatafromtheI/OpinsoftheSoC.In
many test access architectures, the SoC-level TAM wires are divided into fixed-
width TAM partitions [Goel and Marinissen 2002; Huang et al. 2002; Iyengar
et al. 2003b; Larsson and Peng 2002]. In the scenario being considered here, all
wires of a TAM partition belong to the same ATE port, which can be configured
for a predefined scan data rate. TAM optimization methods published in the
literature do not handle the general problem of designing TAM architectures
that are driven by port-scalable ATEs.
The problem of designing a TAM architecture to minimize the SoC test time
hasbeenshownintheliteraturetobeN P-hard[Iyengaretal.2002].Therefore,
efficient heuristic techniques have been developed for SoC test planning and
TAMoptimization[GoelandMarinissen2002;Gonciarietal.2003;Huangetal.
2002; Iyengar et al. 2003b; Larsson and Peng 2002; Zhao and Upadhyaya 2003;
Yoneda et al. 2007; Yu et al. 2007; Xu and Nicolici 2005]. However, it is assumed
in all these methods that at any instant in time, the ATE provides test stimuli
to the SoC at a single data rate. As a result, existing optimization techniques
cannot readily exploit the availability of simultaneous multiple data-transfer
rates from the ATE to the SoC. In this work, we focus on the problem of de-
signing an optimized TAM architecture that can benefit from the availability
of port scalability in ATEs. As in Goel and Marinissen [2002], Iyengar et al.
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[2003b], and Larsson and Peng [2002], we base our TAM design on a test bus
model.
The testing of embedded cores with multiple scan data rates was recently ad-
dressed in Xu and Nicolici [2004a, 2004b], Sehgal et al. [2004], and Sehgal and
Chakrabarty[2007].ThekeyideainXuandNicolici[2004a]istousebandwidth
matchingandtodetermineappropriatescanfrequenciesfortheTAMpartitions
to reduce test time; however, no limits are set on the maximum scan frequen-
cies of the cores. In Sehgal and Chakrabarty [2007], the number of data rates
for the available ATE channels is set to two. The preceding assumptions are
too restrictive in practice. In this article, we consider a more general scenario
in which cores with different scan frequencies can be driven by ATE channels
operating in a data-rate range given by the range of scan frequencies for the
cores.
We optimize the TAM architecture for a set of cores with different maxi-
mum scan data rates. We compare this approach to a baseline case in which
all cores are tested at their maximum scan frequencies. We use an iterative
descent procedure that minimizes the testing time by jointly optimizing the
widths of TAM partitions, TAM frequencies, and assignment of cores to TAM
partitions. We also present a solution to this problem based on integer linear
programming (ILP). Although ILP yields optimal results, it is computation-
ally infeasible for large problem instances. Nevertheless, the ILP model can be
used to evaluate the heuristic for small problem instances. We derive a lower
bound on the SoC testing time and list these bounds for several ITC’02 SoC test
benchmarks [Marinissen et al. 2002]. We also present experimental results for
several ITC’02 benchmark SoCs.
While the testing of multiple cores in parallel in a core-based SoC results in
test schedules with low test times, the concurrent testing of these cores results
inincreasedpowerconsumptionduringtestapplication.Thepermissiblepower
envelope is often exceeded when power constraints are not considered during
test scheduling [Chou et al. 1997]; this can lead to thermal runaway, or cause
severe irreparable damage to the SoC. Testing an SoC can lead to extremely
high switching activity, more than when the circuit is in its functional mode
[Larsson and Peng 2001; Zhao and Upadhyaya 2003]. It is therefore impor-
tant to consider power constraints while designing test schedules for embedded
cores with multiple scan data rates. We therefore formulate a TAM design and
test scheduling problem for cores with different scan frequencies, and we ex-
tend the problem formulation to include constraints that are placed on the test
power.
The rest of this article is organized as follows. In Section 2, we define the test
planning problem that exploits the availability of port-scalable ATEs. We de-
velop an integer linear programming model for this problem and derive a lower
bound on the SoC testing time. In Section 3, we present a scalable heuristic
approach to solve this problem. Experimental results for several ITC’02 bench-
mark SoCs are also presented. Section 4 describes a power-aware heuristic
scheduling method to solve the test planning problem. Experimental results
for the ITC’02 SoC test benchmarks are presented to illustrate the impact of
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powerconstraintsonthetestplanningproblem.Finally,wepresentconclusions
and directions for future work in Section 5.
2. TAM ARCHITECTURE OPTIMIZATION
In this section, we formulate the TAM optimization problem when port-scalable
testers are used. We develop an ILP model to solve this problem and derive a
geometric lower bound on the test time.
Problem Pport−scalable. Given the test-data parameters for N embedded cores
in an SoC, the maximum scan frequency f?
the SoC-level TAM width W determine: (i) the number of TAM partitions B;
(ii)foreachTAMpartition j,thewidthwjandthescanfrequency fj,1 ≤ j ≤ B;
and (iii) the assignment of cores to TAM partitions. The aforesaid assignment
of cores must be such that: (a) the frequency of each TAM partition does not
exceed the maximum frequency of any core assigned to this TAM partition; (b)
the sum of widths of TAM partitions does not exceed the total TAM width W;
and (c) the overall test time of the SoC is minimized.
The test set parameters for each core include the number of primary inputs,
primary outputs, bidirectional I/Os, test patterns, scan chains, and scan-chain
lengths. The cores are assumed hard, that is, the number and length of scan
chains are fixed prior to test planning. These parameters are used to design a
wrapperforthecores.TheDesign WrapperalgorithmfromIyengaretal.[2002]
is used to design a wrapper and determine the testing time for a core for a given
TAMwidth.Notethatifthescanfrequenciesofallcoresareequal, Pport−scalableis
equivalent to the original N P-hard TAM-design problem described in Iyengar
et al. [2002]. Hence Pport−scalableis at least N P-hard.
The testing time of core i on a TAM partition of width wj is expressed as
Ti(wj) = ?(max{sii, soi} · pi+ min{sii, soi})/wj? + pi, where sii, soi, and piare
the maximum scan-in time, maximum scan-out time, and the number of test
patterns for core i, respectively [Marinissen et al. 1998]. The testing time is
expressed in units of clock cycles.
The test time Ti(wj, f ) for core i at frequency f on a TAM partition of width
wj is defined as Ti(wj, f ) = Ti(wj)/f, where the testing time is expressed in
units of μs if f is given in MHz. The overall test time of an SoC is the maximum
of the test time over all TAM partitions. Let xij= 1, if core i is assigned to TAM
j, otherwise xij= 0. The problem Pport−scalablecan now be stated as follows.
Minimize T = maxj{?N
(1)
partition;
(2)
W;
(3) fj= mini{{ f?
A and {0}; and
(4) wj ≤ wmax, 1 ≤ j ≤ B, where wmaxis a user-defined limit on the size of a
TAM partition.
ifor each core i (1 ≤ i ≤ N) and
i=1
Ti(wj)·xij
fj
} subject to the following.
?B
?B
jxij = 1, 1 ≤ i ≤ N, namely, every core is connected to only one TAM
jwj= W, namely, the sum of widths of TAM partitions does not exceed
i·xij}\{0}}, where {A\{0}} denotes the set difference between
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Each TAM partition j has wjwires that are connected to wjtester channels
belonging to the same ATE port. This port is configured to operate at frequency
fj.Thereisanupperlimitonthenumberofchannelsthatcanbeincludedinan
ATE port, hence the width of each TAM partition cannot exceed an upper limit
of wmax. For a typical port-scalable ATE such as the Agilent 93000, wmax= 64
[Khoche 2001].
Next we consider a special case of Pport−scalable which we refer to as
P?
stances of Pport−scalable. A solution to P?
cores and frequencies to TAM partitions. We assume here that TAM parti-
tions have already been determined. We also present an ILP model for this
problem.
The problem P?
niques presented in Chakrabarty [2001]. However, it can be solved exactly for
small problem instances using an ILP model. The solution P?
used to optimally determine the assignment of cores and frequencies to TAM
partitions. Let fijdenote the frequency at which core i is tested if it is assigned
to TAM partition j. Let τij = 1/fij denote the corresponding time period. Let
τ?
ematical programming model for P?
port−scalable. This special case is introduced to optimally solve specific in-
port−scalableaddresses the assignment of
port−scalablecan also be shown to be N P-hard using the tech-
port−scalablecan be
i= 1/f?
ibe the minimum possible period of the scan clock for core i. A math-
port−scalablecan be derived as follows.
Objective: Min. T = maxj{Ti(wj) · xij· τij} subject to the following.
1.
5. wj≤ wmax.
Note that the preceding objective function is nonlinear due to the product
term xij· τij. We linearize it by replacing it with a new integer variable yij
(yij ≥ 0) and adding the following three constraints for every such product
term: (i) yij− Tmax≤ 0, where Tmaxis an upper bound on the minimum time-
period limit for all cores; (ii) −τij+ yij≤ 0; and (iii) τij− yij+Tmax·xij≤ Tmax.
The new variables and constraints yield the following ILP model.
?B
jwj = W; 2. xij· fij ≤ f?
i; 3. f1j = f2j = ··· = fN j; 4.?B
jxij = 1;
Objective: Minimize T = maxj{Ti(wj) · yij} subject to the following.
1.
2. xij· τ?
3. f1j= f2j= ··· = fN j, 1 ≤ j ≤ B;
4. yij− Tmax≤ 0;
5. −τij+ yij≤ 0; and
6. τij− yij+ Tmax· xij≤ Tmax.
We use this ILP model with the TAM-width partitioning approach from
Iyengar et al. [2002] to solve Pport−scalable. The PPAWEnumerate procedure de-
scribed in Iyengar et al. [2002] enumerates unique TAM partitions for given
values of B and W. In this work, we use the PPAWEnumerate procedure with
the ILP model for P?
?B
jwj= W;
i− τij≤ 0;
port−scalable.
ACM Transactions on Design Automation of Electronic Systems, Vol. 13, No. 3, Article 53, Pub. date: July 2008.