Finding Optimum Parallel Coprocessor Design for Genus 2 Hyperelliptic Curve Cryptosystems.
ABSTRACT Hardware accelerators are often used in cryptographic applications for speeding up the highly arithmetic-intensive public-key primitives, e.g. in high-end smart cards. One of these emerging and very promising public-key schemes is based on hyperelliptic curve cryptosystems (HECC). In the open literature only a few considerations deal with hardware implementation issues of HECC. Our contribution appears to be the first one to propose architectures for the latest findings in efficient group arithmetic on HEC. The group operation of HECC allows parallelization at different levels: bit-level parallelization (via different digit-sizes in multipliers) and arithmetic operation-level parallelization (via replicated multipliers). We investigate the trade-offs between both parallelization options and identify speed and time-area optimized configurations. We found that a coprocessor using a single multiplier (D=8) instead of two or more is best suited. This coprocessor is able to compute group addition and doubling in 479 and 334 clock cycles, respectively. Providing more resources it is possible to achieve 288 and 248 clock cycles, respectively.
Conference Proceeding: Parallel architectures for elliptic curve cryptoprocessors over binary extension fields[show abstract] [hide abstract]
ABSTRACT: The general trend of the hardware implementation of elliptic curve cryptography is to increase throughput by designing a variety of algorithms for the kP operation, by optimizing the architectures of the finite field basic operations, and by selecting the most appropriate coordinate system. Point addition and doubling leave few possibilities for parallelism when considering a single kP operation. It is however possible to explore the design space of an elliptic curve cryptoprocessor sharing the field operators among the computations of some different kP operations. In this paper, an analysis of various parallelism schemes is carried on. The obtained parallelism schemes are evaluated with respect to time performance, referring to an effective VLSI technology.Circuits and Systems, 2003 IEEE 46th Midwest Symposium on; 01/2004
Conference Proceeding: Genus Two Hyperelliptic Curve Coprocessor.[show abstract] [hide abstract]
ABSTRACT: Hyperellipticcurvecryptographywithgenuslargerthanone has not been seriously considered for cryptographic purposes because manyexistingimplementationsaresigniflcantlyslowerthanellipticcurve versions with the same level of security. In this paper, the flrst ever complete hardware implementation of a hyperelliptic curve coprocessor isdescribed.Thiscoprocessorisdesignedforgenustwocurvesover F2113. Additionally, a modiflcation to the Extended Euclidean Algorithm is presented for the GCD calculation required by Cantor's algorithm. On average, this new method computes the GCD in one-fourth the time required bythe Extended Euclidean Algorithm.Cryptographic Hardware and Embedded Systems - CHES 2002, 4th International Workshop, Redwood Shores, CA, USA, August 13-15, 2002, Revised Papers; 01/2002
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ABSTRACT: The design of a modular standard basis inversion for Galois fields GF(2<sup>m</sup>) based on Euclid's algorithm for computing the greatest common divisor of two polynomials is presented. The asymptotic complexity is linear with m both in computation time and area requirement, thus resulting in an AT -complexity of O ( m <sup>2</sup>). This is a significant improvement over the best previous proposal which achieves AT -complexity of only O ( m <sup>3</sup>)IEEE Transactions on Computers 09/1993; · 1.38 Impact Factor