Article
Reduction of the selfforces in Monte Carlo simulations of semiconductor devices on unstructured meshes
Computer Physics Communications (Impact Factor: 3.11). 01/2010; 181(1):2434. DOI: 10.1016/j.cpc.2009.08.013
Source: DBLP
ABSTRACT
When using an unstructured mesh for device geometry, the ensemble Monte Carlo simulations of semiconductor devices may be affected by unwanted selfforces resulting from the particle–mesh coupling. We report on the progress in minimisation of the selfforces on arbitrary meshes by showing that they can be greatly reduced on a finite element mesh with proper interpolation functions. The developed methodology is included into a selfconsistent finite element 3D Monte Carlo device simulator. Minimising of the selfforces using the proper interpolation functions is tested by simulating the electron transport in a 10 nm gate length, 6.1 nm body thick, double gate metal–oxide–semiconductor fieldeffect transistor (MOSFET). We demonstrate the reduction in the selfforce and illustrate the practical distinction by showing I–V characteristics for the device.

 "The MC engine in this device simulator considers three anisotropic valleys (Γ, L, and X) with nonparabolic dispersion . The simulations of Si MOSFETs consider all relevant scattering mechanisms [14], [15] including acoustic phonons, intravalley (gtype and f type) and intervalley (ptype) nonpolar optical phonons, interface roughness based on Ando's model [12], and ionized impurity scattering. The simulations of InGaAs MOSFETs consider the electron scattering with polar optical phonons, intervalley and intravalley optical phonons, nonpolar optical phonons, acoustic phonons, interface roughness , interface phonons at the dielectric/semiconductor interface [16], and ionized impurity scattering. "
Article: Monte Carlo simulations of channel scaling to ultimate limit in Si and In0.3Ga0.7As bulk MOSFETs
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ABSTRACT: Monte Carlo device simulations are carried out to analyse electron transport in scaled Si and In0.3Ga0.7As MOSFETs starting from a 25 nm gate length Si and In0.3Ga0.7As MOSFETs monitoring the electron velocity, kinetic energy and sheet density along the channel at a supply voltage of 1.0 V. We have found that while the drive current is scaled Si MOSFETs dramatically increases, the current increase in scaled In0.3Ga0.7As MOSFET is less pronounced. The drive current increases despite the decline of the injection velocity in Si MOSFETs from 15 nm gate length. A principal reason of the current increase is the increase in the velocity at the drain side of the device. 
Article: Monte Carlo simulations of mobility in doped GaAs using selfconsistent Fermi–Dirac statistics
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ABSTRACT: Electron mobility as a function of ionized impurity concentration is calculated in bulk GaAs using ensemble Monte Carlo simulations. The simulations include Fermi–Dirac statistics with selfconsistently calculated Fermi energy, and electron temperature which are then used in static and in random phase approximation (qdependent) screening model and for the Pauli exclusion principle employed after each scattering event. However, when the degeneracy due to the Pauli exclusion principle is considered in the simulations, then electron mobility starts to increase at high doping concentrations demonstrating a breakdown of the model. This breakdown can be prevented by taking into account a change in the semiconductor bandstructure via dopants acting in its lattice. The bandstructure change has been incorporated by increasing electron effective mass which allows us to obtain very good agreement of simulated electron mobility with experimental data.Semiconductor Science and Technology 03/2011; 26(5):055007. DOI:10.1088/02681242/26/5/055007 · 2.19 Impact Factor 
Article: Monte Carlo Study of Ultimate Channel Scaling in Si and In$_{\rm 0.3}$Ga$_{\rm 0.7}$As Bulk MOSFETs
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ABSTRACT: A detailed analysis of nonequilibrium electron trans port in ntype Si and In0 .3 Ga0 .7 As MOSFETs scaled into ultimate limit of 5nm gate length is carried out using ensemble Monte Carlo device simulations. The analysis is based on simulations of ID  VG characteristics for a template, 25nm gate length Si MOSFET compared against previous results from various Monte Carlo de vice codes, and for an equivalent 25nm gate length In0 .3 Ga0 .7 As MOSFET. The transistors are then laterally scaled from a gate length of 25 nm to 20, 15, 10 and 5 nm monitoring the average electron velocity, energy, and sheet density along the channel at a supply voltage of 1.0 V. A degradation of the injection velocity with the scaling of a gate/channel length is observed. While we have found a decrease in the overall electron velocity profile along the Si channel for gate lengths smaller than 10 nm and a decrease in the injection velocity from a gate length of 20 nm, the increase in the intrinsic drain current in the scaling process is continuous thanks to the increasing velocity at the drain side. However, the velocity in the InGaAs channel MOSFETs increases steadily dur ing the scaling but the increase in the intrinsic drain current is less pronounced. This is the result of a source starvation, due to a low density of states in IIIV semiconductors, which cannot provide a large enough electron sheet density in the channel. This effect is partially mitigated by the enhancement of density of states as a proportion of electrons in the source/drain transfers to upper valleys with a larger electron effective mass.IEEE Transactions on Nanotechnology 11/2011; 10(6):14241432. DOI:10.1109/TNANO.2011.2165555 · 1.83 Impact Factor
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