A Design Method of a Regular Expression Matching Circuit Based on Decomposed Automaton

IEICE Transactions on Information and Systems (Impact Factor: 0.21). 02/2012; 95-D(2):364-373. DOI: 10.1587/transinf.E95.D.364
Source: DBLP


This paper shows a design method for a regular expression matching
circuit based on a decomposed automaton. To implement a regular
expression matching circuit, first, we convert a regular expression into
a non-deterministic finite automaton (NFA). Then, to reduce the number
of states, we convert the NFA into a merged-states non-deterministic
finite automaton with unbounded string transition (MNFAU) using a greedy
algorithm. Next, to realize it by a feasible amount of hardware, we
decompose the MNFAU into a deterministic finite automaton (DFA) and an
NFA. The DFA part is implemented by an off-chip memory and a simple
sequencer, while the NFA part is implemented by a cascade of logic
cells. Also, in this paper, we show that the MNFAU based implementation
has lower area complexity than the DFA and the NFA based ones.
Experiments using regular expressions form SNORT shows that, as for the
embedded memory size per a character, the MNFAU is 17.17-148.70 times
smaller than DFA methods. Also, as for the number of LCs (Logic Cells)
per a character, the MNFAU is 1.56-5.12 times smaller than NFA methods.
This paper describes detail of the MEMOCODE2010 HW/SW co-design contest
for which we won the first place award.

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Available from: Hiroki Nakahara, Jul 03, 2014
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