A statement based parallelizing framework for processor-in-memory architectures

Department of Electrical Engineering, National Sun Yat-sen University, Kaohsiung, Taiwan, R.O.C.
Information Processing Letters (Impact Factor: 0.55). 02/2003; 85(3):159-163. DOI: 10.1016/S0020-0190(02)00353-8
Source: DBLP


A statement based parallelizing framework for processor-in-memory architectures was discussed. The Statement-Analysis-Grouping-Evaluation (SAGE) system was proposed to analyze the source program, generate a Weight Partition Dependence Graph (WPG), determine the weight of each block, and then dispatch the most suitable jobs to the host and memory processors. Results showed that quite good speedup was obtained, which even exceeded the computation capability ratio in 1-host and 1-memory processors environment.

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    • "The benefits of statement-based approach are described in [10]. Based on our original SAGE system [11], COSPIM operates in several phases. The first is to decompose the source application into several blocks which contain minimal number of statements in a loop. "
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    ABSTRACT: Processor-in-memory is a new class of computer architecture designed for reducing the performance gap between the processor and the memory. This architecture provides a tightly-coupled heterogeneous environment by integrating different processors in a system. An efficient parallelization and optimization mechanism is necessary for this system to transform the existed applications to achieve better performance. In this paper, we propose a comprehensive framework, COSPIM, based on the statement viewpoint in our early SAGE system. It integrates program decomposition, ETC (expected time to compute) evaluation and scheduling mechanisms together. We describe how COSPIM splits statements and produces schedule to execute on the host processor and the coprocessor simultaneously. The experimental results of this approach are also discussed.
    Proceedings of the 10th WSEAS international conference on Computers; 07/2006
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    ABSTRACT: Continuous improvements in semiconductor technology are supporting new classes of multi-processor system-on-a-chip (MPSoC) architectures that combine extensive processing logic with high-density memory. Such architectures are generally colled processor-in-memory (PIM) or intelligent memory (I-RAM) and can support high-performance computing by reducing the performance gap between the processor and the memory. The PIM architecture combines various processors in a single chip. These processors are characterized by their computation, memory-access, and power consumption capabilities. Therefore, a novel parallelizing system, SAGE II, has be developed to identify their capabilities and dispatch the most appropriate jobs to them in order to exploit the advantages of PIM architectures. This paper provides a new low-power transformation mechanism, called performance-oriented energy reduction scheduling (POERS), to extend the capability of SAGE II system. It can reduce the energy consumption for the processor-in-memory system without losing execution performance. The detailed POERS transformation technique is presented later. The experimental results of several benchmarks are also discussed.
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