Characterization of Thin-Film SOI PIN Diodes from Cryogenic to Above Room Temperatures Using an Explicit I-V Multi-Branch Model

Abstract

A multi-branch model is proposed to describe multiple conduction
mechanisms in thin-film SOI PIN diodes with parasitic series
resistance over a wide operating temperature range, from 90 to
390 K. The model is composed of the parallel combination of three
branches, each of them incorporating a diode and a series
resistance. The model’s unique advantage is its explicit nature
which allows the terminal current to be continuously expressed as
an explicit analytical function of the applied terminal voltage. The
resulting explicit equation is convenient for repetitive simulation
applications as well as for analytic differentiation and integration,
in contrast to conventional models which only allow numerical
solutions. The model’s suitability has been assessed by parameter
extraction and subsequent playback on real SOI PIN diode forward
I-V characteristics.

Full text

Page 1

Characterization of Thin-Film SOI PIN Diodes from Cryogenic to Above Room
Temperatures Using an Explicit I-V Multi-Branch Model



Denise Lugo-Muñoza, Juan Mucia, Adelmo Ortiz-Condea, Francisco J. García-Sáncheza,
Michelly de Souzab, Denis Flandrec, Marcelo A. Pavanellob

a Solid-State Electronics Laboratory, Simón Bolívar University, Caracas 1080, Venezuela
b Department of Electrical Engineering, Centro Universitário da FEI, São Bernardo do
Campo, SP, Brazil
cElectrical Engineering Department, ICTEAM Institute, Université Catholique de
Louvain, Louvain-la-Neuve, Belgium


A multi-branch model is proposed to describe multiple conduction
mechanisms in thin-film SOI PIN diodes with parasitic series
resistance over a wide operating temperature range, from 90 to
390 K. The model is composed of the parallel combination of three
branches, each of them incorporating a diode and a series
resistance. The model’s unique advantage is its explicit nature
which allows the terminal current to be continuously expressed as
an explicit analytical function of the applied terminal voltage. The
resulting explicit equation is convenient for repetitive simulation
applications as well as for analytic differentiation and integration,
in contrast to conventional models which only allow numerical
solutions. The model’s suitability has been assessed by parameter
extraction and subsequent playback on real SOI PIN diode forward
I-V characteristics.


Introduction

PIN (p+-i-n+) diode I-V characteristics are typically modeled, as any other junction, by
using some kind of single-exponential modified Shockley equation which includes the
effect of parasitic series resistance, and parallel shunt resistance if needed. The originally
implicit form of this equation may be made explicit by means of the Lambert function (1)
in the case of only series resistance (2), and also in the case of both series and internal
and external shunt resistances (3). Those analytical solutions are widely used today in
many applications, for example in different kinds of diodes (4-6) and solar cells (7-9).

When modeling real PIN devices with a significant parasitic series resistance however,
a single-exponential equation is usually not enough to adequately describe the forward
I-V characteristics over a wide temperature range, especially at low temperatures (10).
They need to be represented instead by a lumped multi-diode equivalent circuit, such as
the one shown in Figure 1. In the presence of parasitic series resistance, current
conduction is modeled by the summation of multiple-exponential expressions,
corresponding to each of the significant conduction mechanisms present in the device, all
in series with the parasitic series resistance.
ECS Transactions, 39 (1) 171-178 (2011)
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Figure 1. A conventional equivalent circuit of a real PIN diode with multiple diodes and a
single global series resistance.

The total current is then described by the following implicit equation:

∑
=
k
1
⎥
⎦
⎤
⎢
⎣
⎡
⎟⎟
⎠
⎞
⎜⎜
⎝
⎛
−
n
=
N
thk
S
k
vT
ITR
(
V
TITV
(
I
0
)
)(
exp)(), , [1]

where vth=kT/q is the thermal voltage, N is the number of different conduction
mechanisms to be considered in the model, I0k(T) is the temperature dependent reverse
current coefficient corresponding to each kth mechanism, nk(T) is the corresponding
possibly temperature dependent “ideality” factor, and RS(T) is the temperature dependent
parasitic series resistance.

Regrettably Eq. [1] has the severe inherent limitation of not being explicitly solvable
in general for either the terminal current or voltage, save for two notable exceptions: a)
the case of a single exponential (N=1) model whose explicit solutions are well known (3),
and b) the case of a double-exponential (N=2) model where the ideality factors are fixed
quantities, one equal to exactly twice the other (n2=2n1), in which case a quadratic
explicit solution is possible for the terminal voltage (10).

Having an analytically explicit equation to model PIN diodes would be useful, not
only because simulation times could be significantly reduced, but also because such an
equation could be effortlessly differentiated or integrated, a feature that allows to readily
construct other model-derived functions such as the device’s dynamic resistance or its
temperature dependence. With this aim in mind, we propose to avoid the explicit
insolvability of Eq. [1] when modeling PIN diodes by using an alternative multi-
exponential model which does have an explicit solution.


The Model

The equivalent circuit of the proposed model is shown in Figure 2. This model’s I–V
characteristics may be mathematically represented by the following explicit equation for
the current:

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)()()(
)(
)()(
exp
)(
)()
T
(
)(
)
T
(
)(
)()(
exp
)(
)()
T
(
)(
)
T
(
)(
)()(
exp
)(
)()
T
(
)(
)
T
(
),(
000
00
0
00
0
00
0
TITITI
vTn
TITRV
vn
TITR
W
R
vTn
vTn
TITRV
vn
TITR
W
R
vTn
vTn
TITRV
vn
TITR
W
R
vTn
TVI
HML
thH
HH
thH
−
HH
H
thH
thM
MM
thM
MM
M
thM
thL
LL
thL
LL
L
thL
−−
⎥
⎦
⎤
⎢
⎣
⎡
⎟⎟
⎠
⎞
⎜⎜
⎝
⎛
+
+
⎥
⎦
⎤
⎢
⎣
⎡
⎟⎟
⎠
⎞
⎜⎜
⎝
⎛
+
+
⎥
⎦
⎤
⎢
⎣
⎡
⎟⎟
⎠
⎞
⎜⎜
⎝
⎛
+
=
, [2]

where W0 is short hand notation for the principal branch of the Lambert function (1) and
the rest of the parameters are defined as before, with the L, M, and H subindices referring
to the conduction mechanisms that dominate at low, medium, and high forward voltages,
respectively. Notice that the single global series resistance, RS, of Eq. [1], has now been
replaced by three distinct individual series resistances, RL, RM, and RH, placed at each of
the parallel branches associated with the different conduction mechanisms. This feature is
what makes the model analytically solvable.

+
-


Figure 2. Equivalent circuit of the proposed three branch model.

It should be pointed out that conventional model [1] and this alternative model [2],
shown in Figures 1 and 2, respectively, are not mathematically equivalent in a strict sense.
However, as will become evident, there can be a broad range of parameter conditions for
which the correspondence between both models can be excellent. For example we shall
see that in the present case:

111
+≈
HHMLS
RRRRR
11
≈+
. [3]

A word of caution is called for about using Eq. [2] for numerical calculations when the
value of any of the associated individual branch series resistances takes the value of zero.
In that unlikely case, the particular branch where the series resistance goes to zero must
be directly described by the unmodified Shockley equation.

It is worth mentioning here that Eq. [2] resembles the defining equation of a model
proposed by Miranda et al. (11) to express the leakage post-breakdown I-V characteristics
of HfO2/TaN/TiN gate oxide stacks used in MOSFETs. In that unrelated model, the most
relevant post-breakdown conduction mechanisms that arise in the broken gate oxide are
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described by a parallel combination of two opposite-direction connected diodes with
individual series resistances and a shunt leakage path (11). Models which show some
similarity to the present model have also been proposed to describe the current
conduction mechanisms present in poly and multicrystalline solar cells (12-15).


Characterization of real lateral SOI PIN diodes

The present model was used to describe the forward current of experimental lateral
thin-film SOI PIN diodes fabricated using a 150 nm technology from OKI Semiconductor
on a 40 nm thick silicon layer over a 145 nm substrate oxide (16). I-V characteristics
were measured at forward voltages from 0.1 to 1.5 V, using voltage steps of 10 mV, at
several temperatures of interest.

Figure 3 presents the I-V characteristics of a 0.8 μm long, 50 μm wide device
measured at temperatures from 90 to 390 K, with increments of 30 K. As observed, the
resistive shunt loss is negligible in these devices.

10-1
V (V)
0.00.20.40.60.81.01.21.4
I (A)
10-11
10-10
10-9
10-8
10-7
10-6
10-5
10-4
10-3
10-2
T=90 K

390 K
Experimental Data
W=50μ μm
tSi=40nm
toxb=145nm
Li=0.8μ μm

Figure 3. Measured forward I-V characteristics of an experimental 0.8 μm long lateral
SOI PIN diode for a wide range of operating temperatures.

Parameter extraction was performed on these lateral SOI PIN diodes using global
fitting of the logarithm of the alternative model [2] to the measured devices’ I-V
characteristics. The extraction was done in two steps: First, all parameters were
considered to be temperature dependent and their values extracted. Second, the values of
those parameters that exhibited small temperature dependence were fixed and the rest of
the parameters were extracted again. Table I presents the results of this process.

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TABLE I. Extracted Model Parameter Values
Fixed parameter values: nH = nM = 1.2; RM = 150 Ω; RL = 50 kΩ
Temperature dependent parameter values:
I0H (A)
I0M (A)
90
6.85x10-58
1.44x10-55
100
5.30x10-52
3.17x10-50
110
2.99x10-47
7.44x10-46
120
2.49x10-43
3.29x10-42
150
8.72x10-35
3.43x10-34
180
4.16x10-29
8.04x10-29
210
4.81x10-25
5.15x10-25
240
5.51x10-22
3.83x10-22
270
1.41x10-19
5.16x10-20
300
1.21x10-17
2.45x10-18
330
4.50x10-16
5.42x10-17
360
8.61x10-15
1.07x10-15
390
1.09x10-13
1.40x10-14
T (K)
I0L(A)
1.00x10-21
2.93x10-21
8.02x10-21
2.71x10-20
5.57x10-19
8.85x10-18
9.55x10-17
1.02x10-15
5.29x10-15
2.95x10-14
1.46x10-13
5.70x10-13
2.42x10-12
nL
3.89
3.59
3.35
3.17
2.74
2.46
2.25
2.13
1.97
1.88
1.83
1.78
1.82
RH (Ω)
11.10
11.92
12.57
13.07
14.25
14.99
15.74
16.05
16.83
17.45
18.04
18.59
19.23

Figure 4 presents the model playbacks obtained with the extracted model parameters
which were used to calculate the current and its three branch components, versus the
normalized applied forward voltage, plotted over the original measured data (represented
by symbols) of the experimental 0.8 μm diode at three representative temperatures.

10-1
390 K150 K
V/vth
0 50 100150200
I (A)
10-11
10-10
10-9
10-8
10-7
10-6
10-5
10-4
10-3
10-2
T=90 K
nL =3.9
nM =1.2
nH =1.2
2.7
1.2
1.2
1.8
1.2
1.2

Figure 4. Measured (lines) and model playback (symbols) of the current of the
experimental 0.8 μm long lateral SOI PIN diode as a function of normalized applied
forward voltage at three representative temperatures.

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Figures 5, 6 and 7 present the extracted reverse current coefficients, low voltage
conduction ideality factor and high voltage series resistance parameters, respectively. An
exponential 1/T dependence is observed for the reverse current coefficients in the
medium and high forward voltage conduction regions, where the ideality factors have
fixed values (nH = nM = 1.2). On the other hand, the low forward voltage conduction
region exhibits a distinctly different behavior for both the reverse current coefficient and
the ideality factor, as can be predicted by simple observation of Figure 4. The
temperature dependence of the parasitic series resistance is represented by the high
forward voltage resistance behavior (RH), which shows a slight increase in resistance with
temperature.

Figure 8 presents the temperature dependence of the terminal voltage at four
representative values of forward current, chosen within each of the three distinctive low,
medium and high forward conduction regions, plus the upper series resistance dominated
conduction region. As expected, each curve exhibits a different quasi-linear temperature
dependence of the forward voltage. Also, the almost flat curve corresponding to the
region where the parasitic series resistance is dominant indicates an almost temperature
independent behavior in this region.

10-10
10-11
103/T (K-1)
246810 12
I0H (A)
10-60
10-55
10-50
10-45
10-40
10-35
10-30
10-25
10-20
10-15
10-10
103/T (K-1)
24681012
I0M (A)
10-60
10-55
10-50
10-45
10-40
10-35
10-30
10-25
10-20
10-15
103/T (K-1)
2468 1012
I0L (A)
10-22
10-21
10-20
10-19
10-18
10-17
10-16
10-15
10-14
10-13
10-12
(a)
(b)(c)

Figure 5. Extracted values of the temperature dependent reverse current coefficient
parameters corresponding to the three conduction mechanisms considered.

4.5
T (K)
50 100 150 200 250 300 350 400 450
nL
1.5
2.0
2.5
3.0
3.5
4.0
103/T (K-1)
24681012
nL
1.5
2.0
2.5
3.0
3.5
4.0
4.5

Figure 6. Temperature dependence of the extracted low voltage conduction ideality factor
parameter.

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103/T (K-1)
24681012
RH (Ω Ω)
10
12
14
16
18
20
T (K)
50 100 150 200 250 300 350 400 450
RH (Ω Ω)
10
12
14
16
18
20

Figure 7. Temperature dependence of the extracted high voltage series resistance
parameter (RH ≈ RS).

1.6
T (K)
50 100 150 200 250 300 350 400 450
V (V)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4

W=50μ μm
tSi=40nm
toxb=145nm
Li=0.8μ μm
1.7x10-2 A
1.0x10-3 A
6.8x10-6 A
3.4x10-11 A

Figure 8. Temperature dependence of the voltage at four values of forward current,
representative of each of the three low, medium and high forward conduction regions,
plus the upper series resistance dominated conduction region (square, diamond, triangle,
and circle symbols, respectively).

Conclusions

The close match observed between the experimental and the playback I-V
characteristics corroborates the excellent suitability of this multi-branch model approach
to describe the lateral thin-film SOI PIN diodes over a wide temperature range, from
cryogenic to above room temperatures. The appropriate representation of these
characteristics is very important for the many devices’ applications. In addition to their
use as Temperature Sensors, forward biased PIN diodes are commonly used as Current
Controlled Linear Resistors for RF applications (17). Moreover, lateral SOI PIN diodes
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are widely used in various “gated-diode” configurations (18,19) as Gate-controlled Field-
Effect diodes (20) for clamping applications in ESD protection. The unique explicit
nature of the proposed model allows for the analytically explicit description of other
model-derived functions, such as the dynamic resistance or the temperature dependence
that can be very useful in future device analysis, but are beyond the scope of the present
characterization.

ACKNOWLEDGMENTS

The authors wish to express their gratitude for the support received from CNPq
PROSUL international cooperation (Brazil) and the Office of the Dean of Research of
Simón Bolívar University (Venezuela). M. A. Pavanello and M. de Souza would like to
thank the brazilian funding agencies CAPES and CNPq for the financial support.

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