Article
Informed Dynamic Scheduling for Belief-Propagation Decoding of LDPC Codes
03/2007;
Source: arXiv
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Conference Proceeding: High throughput low-density parity-check decoder architectures
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ABSTRACT: Two decoding schedules and the corresponding serialized architectures for low-density parity-check (LDPC) decoders are presented. They are applied to codes with parity-check matrices generated either randomly or using geometric properties of elements in Galois fields. Both decoding schedules have low computational requirements. The original concurrent decoding schedule has a large storage requirement that is dependent on the total number of edges in the underlying bipartite graph, while a new, staggered decoding schedule which uses an approximation of the belief propagation, has a reduced memory requirement that is dependent only on the number of bits in the block. The performance of these decoding schedules is evaluated through simulations on a magnetic recording channelGlobal Telecommunications Conference, 2001. GLOBECOM '01. IEEE; 02/2001 -
Conference Proceeding: Shuffled belief propagation decoding
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ABSTRACT: In this paper, we propose a shuffled version of the belief propagation (BP) algorithm for the decoding of low-density parity-check (LDPC) codes. We show that when the Tanner graph of the code is acyclic and connected, the proposed scheme is optimal in the sense of MAP decoding and converges faster (or at least no slower) than the standard BP algorithm. Interestingly, this new version keeps the computational advantages of the forward-backward implementations of BP decoding. Both serial and parallel implementations are considered. We show by simulation that the new schedule offers better performance/complexity trade-offs.Signals, Systems and Computers, 2002. Conference Record of the Thirty-Sixth Asilomar Conference on; 12/2002 -
Conference Proceeding: Optimized Message Passing Schedules for LDPC Decoding
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ABSTRACT: The major drawback of the LDPC codes versus the turbo-codes is their comparative low convergence speed: 25-30 iterations vs. 8-10 iterations for turbo-codes. Recently, Hocevar showed by simulations that the convergence rate of the LDPC decoder can be accelerated by exploiting a `turbo-scheduling' applied on the bit-node messages (rows of the parity check matrix). In this paper, we show analytically that the convergence rate for this type of scheduling is about two times increased for most of the regular LDPC codes. Second we prove that `turbo-scheduling' applied on the rows of the parity check matrix is identical belief propagation algorithm as standard message passing algorithm. Furthermore, we propose two new message passing schedules: 1) a turbo-scheduling is applied on the check-node messages (columns of the parity check matrix); and 2) a hybrid version of both previous schedules where the turbo-effect is applied on both check-nodes and bit-nodes. Frame error rate simulations validate the effectiveness of the proposed schedulesSignals, Systems and Computers, 2005. Conference Record of the Thirty-Ninth Asilomar Conference on;
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Keywords
check nodes
convergence speed
factor graph
implementability issues
informed scheduling solves
iterations
iterative belief-propagation
large numbers
Low-Density Parity-Check
message-passing
paper presents practical scheduling strategies
pre-update information
sequences
sequential scheduling
Simulation results
standard sequential schedules
standard trapping
traditional message-passing schedule
variable nodes