arXiv:0806.2942v1 [cond-mat.mtrl-sci] 18 Jun 2008
InAs Nanowire MOS Capacitors
Stefano Roddaro, Kristian Nilsson, Gvidas Astromskas,
Lars Samuelson, and Lars-Erik Wernersson
the Nanometer Structure Consortium,
Lund University, P.O. Box 118, 22100 Lund, Sweden
Olov Karlstr¨ om and Andreas Wacker
the Nanometer Structure Consortium, Lund University,
P.O. Box 118, 22100 Lund, Sweden and
Mathematical Physics, Lund University,
P.O. Box 118, 22100 Lund, Sweden
(Dated: June 19, 2008)
We present a capacitance-voltage study for arrays of vertical InAs nanowires. MOS capacitors
are obtained by insulating the nanowires with a conformal 10nm HfO2layer and using a top Cr/Au
metallization as one of the capacitor’s electrodes. The described fabrication and characterization
technique enables a systematic investigation of the carrier density in the nanowires as well as of
the quality of the MOS interface.
The development of wrap-gate nanowire (NW) field effect transistors (FETs) is opening
promising perspectives for future high-performance electronic devices [1, 2]. NWs allow the
integration of semiconductor materials with reduced lattice-matching constraints [3, 4] and
offer the intriguing possibility of growing III-V structures on Si substrates, thus introducing
high-mobility and optically-active elements on a Si platform . However, many of the key
parameters of the NWs such as doping level and carrier distribution are still difficult to
determine in a direct and conclusive way. For conventional FETs it is possible to take ad-
vantage of capacitance-voltage (CV) characterizations to determine, in a precise way, carrier
concentration and interface properties of planar metal-oxide-semiconductor (MOS) stacks.
Similar measurements have been largely unavailable for semiconductor NWs because of the
extremely small capacitance of these nanostructures (down to aF). Recent experimental
studies showed that such a small capacitance can be detected using bridge measurements
together with appropriate screening . Here we demonstrate CV measurements of small
arrays of vertical NWs, where the NW capacitance can be easily separated from the para-
sitic capacitance between the gate connection and the conducting substrate. Our vertical
fabrication protocol is scalable and thus enables parallel processing, which is crucial for a
systematic investigation of the device properties.
The device structure is presented in Fig. 1. NW arrays (Fig. 1a) were obtained by self-
assembled growth in a chemical beam epitaxy (CBE) system. NW fomartion is guided by
gold nanoparticles that are deposited on a doped InAs (111)B substrate . A number of
arrays was defined in parallel with various nanoparticle sizes to study radius dependance.
For the present investigation 5 different groups of 15 nominally identical NW arrays were
fabricated with an average radius rNW of 23.0nm, 25.0nm, 26.5nm, 28.5nm and 30.0nm,
respectively. Panel (b) shows a typical radius distribution in a single 11 × 11 array with a
standard deviation of about 4.0nm. The device structure is sketched in panel (c) and (d):
NWs were first insulated by a conformal HfO2coating (purple) by atomic layer deposition
(125 cycles at 250◦C, corresponding to dox≈ 10nm); the top electrode encapsulating the
NWs was then fabricated by sputtering a Cr/Au bilayer (nominal 20/25nm). A polymeric
film of S1813 from Shipley with a thickness of about 1µm (green) was used as a lifting
layer in order to increase the ratio CNW/C0between the NW capacitance CNW and stray
capacitance C0in our devices. Single devices were finally defined by UV lithography and
metal etching of 30 × 45µm2gate pads.
f = 20MHz
δV = 20mV
FIG. 1: (a) Scanning electron micrograph of a 11 × 11 InAs nanowire array (tilt angle 52◦).
(b) Typical radius distribution in the array.(c) and (d) Details of the device structure. (e)
Representative C(V ) scan from −3V to +3V (red) and return (green) compared with a bare pad
The NW capacitance was measured at room temperature in a Cascade probe station
system equipped with an Agilent 4294A impedance analyzer. The complex impedance Z =
|Z|eiθwas measured using a small AC modulation δV = 20mV on top of a DC bias V
in the range [−3V,+3V]. A simplified scheme of the biasing configuration is shown in
the inset to Fig. 1(e). The measured Z was found to be mostly capacitive (θ ≈ −90◦)
and was interpreted in terms of a series RC model with Z = R − i/ωC. Such a simple
model is appropriate in our case and experimental Z(ω,V ) data for V>
∼+1V yield a
frequency-independent and well-defined C(V ). The frequency evolution of Z(ω,V ) in the
depletion regime for V < 0 is less trivial as expected due to the increasing NW resistance,
to the activation of slow trap states at the interfaces and to effects of inversion in the InAs
semiconductor. In particular, the increasing importance of RC constants close to the pinch-
off is a peculiarity of our cylindrical geometry and sets a qualitative difference with respect
to conventional planar MOS capacitors. The plot in Fig. 1(e) shows typical C(V ) sweeps
obtained on devices from the group rNW = 26.5nm at a frequency f = 20MHz: we mark
the sweep going from negative to positive V as C↑(V ) (red) and C↓(V ) for the opposite
sweep direction (green). The capacitance saturates at negative voltages to C0≈ 70 − 80fF,
grows sharply across V ≈ 0V and flattens again for V > 1V in the accumulation regime.
Differently from conventional MOS capacitors, here we expect the NW to become insulating
in the depletion limit and C to approach zero instead of a finite depletion capacitance.
Indeed, here the observed saturation C → C0corresponds to the NW depletion, as proved
by comparison with four bare pads of the same geometry (black curve). The presence of C0
is not linked to the NWs and it is rather due to both the parallel capacitance between the
pad and the substrate as well as the one between the probe tips and the substrate.
Hysteresis effects are analyzed in Fig. 2. In the first panel, the shift between the ca-
pacitances measured in the two opposite sweep directions is barely visible on small (less
than 1V) sweep ranges while it increases for larger V swings. C↓(V ) curves do not depend
strongly on the DC sweep swing while C↑(V ) curves tends to move towards higher C values
(or lower V values, for a given C) when the sweep is extended from ±0.5V up to ±3.0V.
The shift between C↑and C↓does not depend strongly on the sweep speed (about 150mV/s
in our case) and time-dependent measurements indicate that capacitances tend to relax from
C↑(V ) towards C↓(V ) on a timescale τ ≈ 30mins. We conclude that C↓(V ) results from
an equilibrium distribution of charges at the capacitor’s interfaces while a long-lived out-of-
equilibrium distribution is present along C↑(V ). This effect can be evaluated quantitatively
in a simple way if one assumes that trapped charges are located exactly at the NW surface:
in that case the addition of a surface charge density ∆σswill shift an ideal C(V ) curve as
Cmeas(V ) = C(V + SNW× ∆σs/Cox) (1)
where SNW= 2πrNWLNWand LNWare the surface and length of the gated NW, respectively,
while Coxis the oxide capacity 2πεLNW/log(1 + dox/rNW). The value of ∆σsdepends on
the biasing history of the device, thus we obtain the different hysteresis cycles for different
sweep swings. Figure 2b shows the average surface charge
-2.0 -1.0 0.0 1.0 2.0
0.0 0.2 0.4 0.6 0.8 1.0 0.0 0.2 0.4 0.6 0.8 1.0
Biasing swing (V)
FIG. 2: (a) Evolution of the hysteresis cycle for increasing gate swings from [−0.5,+0.5]V up to
[−3.0V,+3.0]V. (b) Charge loop integrals ?∆σs? for different device geometries as a function of
the biasing swing around 0V.
where ∆C is the capacitance swing of the cycle and we used an average LNW = 680nm
(from SEM imaging of the devices), ε = 15ε0[8, 9] and Cox= 1.78fF. The plot reports
the loop integrals for the various device groups we studied: for V swings below ≈ 0.5V we
obtain ?∆σs? < 1.0 × 1011cm−2, which seems very promising for device applications of NW
as wrap-gate transistors . Note however, that the hysteresis in surface charge becomes
much larger if the bias sweep extends further into the depletion region.
To further analyze the data, we performed detailed calculations for the capacitance on
the basis of a Poisson-Schr¨ odinger code similar to Refs. [11, 12]. Fig. 3(a) shows the unit
length capacitance for three different doping densities Nd of the wire, which are treated
as a homogeneous positive background charge. The experimental data shown correspond
to the assumption that 90 out of 121 wires are actually properly connected in the device:
this scaling is required in order to match the geometry-set capacitance in accumulation and
is not unreasonable given the present device parameters. The best fit is obtained using a
doping of 2.0 × 1018cm−3: the curve at 1.0 × 1018cm−3rolls down too quickly with the
voltage V ; differently at Nd= 4.0 × 1018cm−3the valence bands cross the Fermi level at
the interface before the conduction band is completely depleted (0.54eV was used as the
wurtzite InAs gap ) and screening effects due to inversion are expected to show up,
inconsistently with observations. It is interesting to note that all the fit curves in Fig. 3a
10 20 30 40 50
10 20 30 40 50
10 20 30 40 50
Nd = 1.0x1018cm-3
Nd = 2.0x1018cm-3
Nd = 4.0x1018cm-3
Nd = 4.0x1018cm-3
Nd = 1.0x1018cm-3
Nd = 2.0x1018cm-3
FIG. 3: (a) Theoretical fit of the dataset C↓(V ) of Fig. 1(e) using three different carrier densities.
The band bending (black) and electron density (red) at the three different points along the blue
line at doping Nd= 2 × 1018cm−3are reported in the lower panels for accumulation (b), flatband
(c) and depletion (d) conditions.
fall nearly 50% short of the classical Cox= 2.61fF (for a 1.0µm length, rNW= 26.5nm and
dox= 10nm) even in the accumulation regime at V ≈ +3.0,V. This is an effect of quantum
capacitance is due to the narrow radius of the NW with respect to the screening length.
Lower panels indicate the corresponding conduction band diagram Ec(r) in the capacitor in
the accumulation (b), flatband (c) and depletion (d) regimes: the corresponding positions
along the C(V ) fit are indicated in the top panel. We obtained best agreement assuming
the gate bias V to be 0.39V larger than the calculated electrostatic potential at the gate.
This shift can be attributed to the difference between the work function of Cr (4.5eV) and
the electron affinity of InAs (4.9eV for zincblende lattice) as well as negative fixed charges
(with areal density ∼ 8 × 1012cm−2) trapped in the oxide. As the electron affinity of the
nanowire is uncertain due to the uncommon wurtzite structure exhibiting a larger band
gap , this estimate for the density of fixed charges is probably too large. It is crucial to
note here that we assumed that only electrons in the conduction band are able to contribute
to the C(V ) at our frequency. We interpret the discrepancy between fit and experiments
for V < 0V as due to the effect of screening of slow trap states in the InAs gap , which
indeed start becoming important at V ≈ 0V in our simulations. Consistently with this
interpretation, we observed experimentally that such discrepancies becomes larger as the
frequency is decreased and a clear C(V ) step develops, similarly to what has been reported
in previous studies on planar structures .
In conclusion we have demonstrated a technique for capacitance-voltage characterizations
of arrays of vertical InAs NWs. Our analysis allows evaluating the role of surface states as
well as yields an estimate of the doping in the NW, thanks to a detailed comparison with
Poisson-Schr¨ odinger simulations. Preliminary results indicate promising device parameters
in view of the application of wrap-gate NWs as high-performance transistors.
This work was supported by the Swedish Research Council, the Swedish Foundation for
Strategic Research, the EU-project NODE 015783, the Knut and Alice Wallenberg Founda-
tion and the Italian Ministery of University and Research.
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