InAs Nanowire MOS Capacitors

Source: arXiv


We present a capacitance-voltage study for arrays of vertical InAs nanowires. MOS capacitors are obtained by insulating the nanowires with a conformal 10nm HfO2 layer and using a top Cr/Au metallization as one of the capacitor's electrodes. The described fabrication and characterization technique enables a systematic investigation of the carrier density in the nanowires as well as of the quality of the MOS interface.

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Available from: Gvidas Astromskas, Nov 13, 2012
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    ABSTRACT: The magnitude and impact of the parasitic capacitances in a vertical InAs nanowire transistor consisting of a matrix of nanowires is evaluated. A simple transistor model is fitted to experimental I–V characteristics and the influence of the parasitic components on the transistor performance for different structures is investigated. Simulations of the S-parameters indicate an intrinsic fT of about 690GHz for 50nm LG. We show that fT reaches 56% of the intrinsic value in an optimized transistor structure with closely spaced nanowires and that a high wire density is more efficient to reduce the parasitics than to pattern the electrodes. Finally, the analytical model is used to demonstrate the operation and to simulate the performance of ring-oscillators.
    Solid-State Electronics 12/2010; 54(12):1505-1510. DOI:10.1016/j.sse.2010.06.017 · 1.50 Impact Factor