Miguel Morales-Sandoval

Computer Architecture, Computer Communications (Networks), Computer Security and Reliability

PhD Computer Science
14.51

Publications

  • Miguel Morales-Sandoval, Arturo Diaz-Perez
    9th WISTP International Conference on Information Security Theory and Practice (WISTP'2015) Heraklion, Crete, Greece. 24--25 August, 2015, Proceedings; 01/2015
  • Miguel Morales-Sandoval, Arturo Diaz-Perez
    9th WISTP International Conference on Information Security Theory and Practice (WISTP'2015) Heraklion, Crete, Greece. 24--25 August, 2015, Proceedings; 01/2015
  • 2014 9th International Conference for Internet Technology and Secured Transactions (ICITST), London, England; 12/2014
  • Morales-Sandoval, Vega-Castillo, Diaz-Perez
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    ABSTRACT: This work describes the analysis, design, and implementation of a secure scheme for storage, retrieval, and fine-grained sharing of digital documents in cloud computing using mobile devices. Confidentiality of digital documents stored in public clouds from a mobile device is achieved by implementing the digital envelope concept. Data are encrypted using AES, and the session key is encrypted using ciphertext-policy attribute based encryption (CP-ABE). CP-ABE also provides access control mechanisms at a fine-grain level, allowing the decryption of the AES key only to those users having the correct set of attributes. The encryption and decryption processes are carried out in a mobile device that interacts with a cloud provider, a trust server, and a key server. For practical implementation of CP-ABE, the Tate pairing was used on elliptic curves type A and F over prime fields, using affine and projective coordinates for the security levels 80, 112, and 128 bits. After evaluating the proposed system for different CP-ABE implementation options, it was observed that the elliptic curves type A allow execution times 18 times faster compared with the use of elliptic curves type F, achieving processing times that ensures the deployment of the proposed secure scheme.
    Information Security Journal A Global Perspective 04/2014; 23. DOI:10.1080/19393555.2014.891282
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    ABSTRACT: Digital fingerprinting is a technique that consists of inserting the ID of an authorized user in the digital content that he requests. This technique has been mainly used to trace back pirate copies of multimedia content such as images, audio, and video. This study proposes the use of state-of-the-art digital fingerprinting techniques in the context of restricted distribution of digital documents. In particular, the system proposed by Kuribayashi for multimedia content is investigated. Extensive simulations show the robustness of the proposed system against average collusion attack. Perceptual transparency of the fingerprinted documents is also studied. Moreover, by using an efficient Fast Fourier Transform core and standard computer machines it is shown that the proposed system is suitable for real-world scenarios.
    PLoS ONE 12/2013; 8(12):e81976. DOI:10.1371/journal.pone.0081976 · 3.53 Impact Factor
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    M. Morales-Sandoval, C. Feregrino-Uribe, P. Kitsos, R. Cumplido
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    ABSTRACT: Montgomery Multiplication is a common and important algorithm for improving the efficiency of public key cryptographic algorithms, like RSA and Elliptic Curve Cryptography (ECC). A natural choice for implementing this time consuming multiplication defined on finite fields, mainly over GF(2m)GF(2m), is the use of Field Programmable Gate Arrays (FPGAs) for being reconfigurable, flexible and physically secure devices. FPGAs allow the implementation of this kind of algorithms in a broad range of applications with different area–performance requirements. In this paper, we explore alternative architectures for constructing GF(2m)GF(2m) digit-serial Montgomery multipliers on FPGAs based on Linear Feedback Shift Registers (LFSRs) and study their area–performance trade-offs. Different Montgomery multipliers were implemented using several digits and finite fields to compare their performance metrics such as area, memory, latency, clocking frequency and throughput to show suitable configurations for ECC implementations using NIST recommended parameters. The results achieved show a notable improvement against FPGA Montgomery multiplier previously reported, achieving the highest throughput and the best efficiency.
    Computers & Electrical Engineering 02/2013; 39(2):542–549. DOI:10.1016/j.compeleceng.2012.08.010 · 0.99 Impact Factor
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    ABSTRACT: In this paper a novel GF(2(m)) multiplier based on Karatsuba-Ofman Algorithm is presented. A binary field multiplication in polynomial basis is typically viewed as a two steps process, a polynomial multiplication followed by a modular reduction step. This research proposes a modification to the original Karatsuba-Ofman Algorithm in order to integrate the modular reduction inside the polynomial multiplication step. Modular reduction is achieved by using parallel linear feedback registers. The new algorithm is described in detail and results from a hardware implementation on FPGA technology are discussed. The hardware architecture is described in VHDL and synthesized for a Virtex-6 device. Although the proposed field multiplier can be implemented for arbitrary finite fields, the targeted finite fields are recommended for Elliptic Curve Cryptography. Comparing other KOA multipliers, our proposed multiplier uses 36% less area resources and improves the maximum delay in 10%.
    Advances in Electrical and Computer Engineering 01/2013; 13(2-2):3-10. DOI:10.4316/AECE.2013.02001 · 0.64 Impact Factor
  • Miguel Morales-Sandoval, Arturo Diaz-Perez
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    ABSTRACT: This work describes a compact FPGA hardware architecture for computing modular multiplications over GF(p) using the Montgomery method, suitable for public key cryptography for embedded or mobile systems. The multiplier is parameterizable, allowing to evaluate the hardware design for different prime fields using different radix of the form β = 2k. The design uses only three k x k multipliers and three 2k-bit adders. The hardware organization of the multiplier maximizes the use of the multipliers processing iteratively the multiplicand, multiplier and modulus. The parametric design allows to study area-performance trade offs, in order to meet system requirements such as available resources, throughput, and efficiency. The proposed multiplier achieves a 1024-bit modular multiplication in 15.63 μs using k = 32. Compared to the most compact FPGA implementation previously reported, our proposed design uses 79% less FPGA resources with better efficiency expressed as Mbps/Slice.
    Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI; 01/2013
  • Miguel Morales-Sandoval, Arturo Diaz-Perez
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    ABSTRACT: This work describes FPGA hardware architectures of GF(2m) multipliers being more compact than a bit-serial multiplier and outperforming software counterparts. The proposed multiplier is more compact than a hardware implementation of the bit-serial approach, considered the most compact one. Also, the designs proposed still outperform software counterparts. For field multiplication, the multiplicand and modulus are parsed in digits of size d while the multiplier is parsed in digits of size D. Thus, the area complexity of the multiplier is mainly determined by the digits {D, d}, not by the order of the finite field m, which affects only the latency and thus the throughput. This approach allows to implement GF(2m) multipliers for any finite field with practically the same amount of FPGA resources. Several multiplier versions were implemented using different combinations for {D, d} in order to find the most compact designs while achieving better performance and efficiency than a bit-serial multiplier. From a hardware implementation in the xc3s1500 FPGA for the finite field GF(2233), the most efficient multiplier is obtained using the digits {D=6, d= 12}, requiring 70% less area resources than a bit-serial multiplier.
    Proceedings of the 16th Euromicro Conference on Digital System Design; 01/2013
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    ABSTRACT: This work reports an efficient and compact FPGA processor for the SHA-256 algorithm. The novel processor architecture is based on a custom datapath that exploits the reusing of modules, having as main component a 4-input Arithmetic-Logic Unit not previously reported. This ALU is designed as a result of studying the type of operations in the SHA algorithm, their execution sequence and the associated dataflow. The processor hardware architecture was modeled in VHDL and implemented in FPGAs. The results obtained from the implementation in a Virtex5 device demonstrate that the proposed design uses fewer resources achieving higher performance and efficiency, outperforming previous approaches in the literature focused on compact designs, saving around 60% FPGA slices with an increased throughput (Mbps) and efficiency (Mbps/Slice). The proposed SHA processor is well suited for applications like Wi-Fi, TMP (Trusted Mobile Platform), and MTM (Mobile Trusted Module), where the data transfer speed is around 50 Mbps.
    Computers & Electrical Engineering 01/2013; DOI:10.1016/j.compeleceng.2013.11.014 · 0.99 Impact Factor
  • A.C. Reyes, A.K.V. Castillo, M. Morales-Sandoval, A. Diaz-Perez
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    ABSTRACT: This work presents an evaluation of different software implementations of algorithms to compute the most demanding operation in cryptographic schemes based on Elliptic Curve Cryptography (ECC), the scalar multiplication. Five different methods were studied, including traditional and more sophisticated methods for elliptic curve cryptography defined over prime and binary fields. For evaluation, the key generation algorithm in ECC consisting on a single scalar multiplication was implemented on a P500h LG smarthphone, which includes an ARM processor running at 600MHz. Both execution time and memory usage was evaluated. It was found that in general, scalar multiplication runs 8 times faster for ECC defined over prime fields, being the NAF the best performer method. For ECC over binary fields, the best performer method was wNAF. The results presented in this work could help a designer to select the most appropriate method when implementing ECC-based cryptographic schemes such as encryption or digital signatures on mobile devices like smartphones, meeting implementation requirements in terms of execution time and memory usage.
    Electronics, Communications and Computing (CONIELECOMP), 2013 International Conference on; 01/2013
  • 23rd International Conference on Electronics, Communications and Computers, CONIELECOMP 2013; 01/2013
  • Proceedings of the 8th International Workshop on Reconfigurable Communication-centric Systems-on-Chip; 01/2013
  • Miguel Morales-Sandoval, Arturo Diaz-Perez
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    ABSTRACT: This work describes novel hardware architectures for GF(2k) multipliers using a digit-digit approach. Contrary to the bit-serial and digit-serial approaches previously addressed in the literature, we consider the partition of the multiplier, multiplicand and modulus in several digits and execute a field multiplication in an iterative way, like in a software implementation but exploiting the parallelism in the operations. We focused on parametric designs that allow to study area-performance trade offs when the multipliers are implemented in FPGAs. This study would guide a designer to select the most appropriate configuration based on the digits sizes in order to meet system requirements such as available resources, throughput, and efficiency. Although the proposed multiplier can be implemented for any finite field of order k, we provide implementation results for GF(2163) and GF(2233), two recommended finite fields for elliptic curve cryptography. For specific digit sizes, our proposed digit-digit multiplier uses considerably less area than a bit-serial multiplier with a penalization in the timing. Compared to a digit-serial implementation, area resources can be saved with still an improvement in the timing respect to a bit-serial implementation.
    Proceedings of the 23rd International Conference on Field Programmable Logic and Applications; 01/2013
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    ABSTRACT: Hash function algorithms are widely used to provide security services of integrity and authentication, being SHA-2 the latest set of hash algorithms standardized by the US Federal Government. The main computation block in SHA-2 algorithms is governed by a loop with high data dependence for which several implementation strategies are explored in this work as well as designs efficiently mapped to hardware architectures. Four new different hardware architectures are proposed to improve the performance of SHA-256 algorithms, reducing the critical path by reordering some operations required at each iteration of the algorithm and computing some values in advance, as possible as data dependence allows. The proposed designs were implemented and validated in the FPGA Virtex-2 XC2VP-7. The achieved results show a significant improvement on the performance of the SHA-256 algorithm compared to similar previously proposed approaches, obtaining a throughput of 909Mbps and an improved efficiency of 0.713Mbps/slice.
    Microprocessors and Microsystems 01/2012; DOI:10.1016/j.micpro.2012.06.007 · 0.60 Impact Factor
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    ABSTRACT: Digital image segmentation is one of the most important stages in the implementation of an Automatic Fingerprint Identification System. This work describes a strategy for image segmentation of latent fingerprints using a proper combination of operators achieving better results than other approaches reported in the literature. Latent fingerprint images are low quality images that make more difficult the segmentation process. The proposed segmentation strategy is based on the gradient magnitude of the image and the detection of regions. This strategy was implemented in Matlab and Java, and was tested using fingerprint images of the Fingerprint Verification Competition databases, which are commonly used for these purposes. The results achieved show a significant improvement compared with representative algorithms of literature, such as those based on the variance of image.
  • K Vega-Castillo, A Cortina-Reyes, M Morales-Sandoval
    01/2012; 10(1):22-29.
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    M Morales-Sandoval, M A Nuño-Maganda
    01/2012; 9(1):1-14.
  • E. Garcia Amaro, M. A. Nuno-Maganda, M. Morales-Sandoval
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    ABSTRACT: Biometric identification (BI) is one of the most explored topics in recent years. One of the most important techniques for BI is face recognition. Face recognition systems (FRSs) are an important field in computer vision, because it represents a non-invasive BI technique. In this paper, a FRS is proposed. In the first step, a face detection algorithm is used for extracting faces from video frames (training videos) and generating a face database. In a second step, filtering and preprocessing are applied to face images obtained in the previous step. In a third step, a collection of machine learning algorithms are trained using as input data the faces obtained in the previous step. Finally, the classifiers are used for classify faces obtained from video frames (test videos). The obtained results shows the suitability of this approach for analyzing large collections of videos where previous face labels are not available.
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    ABSTRACT: Since mobile devices were conceived and commercialized, their market has grown exponentially, so as its problems related to secure data residing in them. Elliptic curve cryptography (ECC) is an approach to public key cryptography (PCK) based on the algebraic structure of elliptic curves over finite fields. It represents the most suitable choice for implementing cryptography in mobile devices since it uses smaller key sizes compared with others traditional public key cryptosystems without decreasing the security level. In this work we present the design of software modules for ECC over .Net Compact Framework (.Net CF) 3.5 well suited for mobile and embedded devices with Windows CE as operating system. The main cores are modules for finite field arithmetic and elliptic curve cryptographic schemes defined over the prime field Zp. These modules are not available neither in the programming language nor the .Net CF. We evaluated the performance of our implementations using the Personal Digital Assistant devices IPAQ 116 and Handheld HP 216, using elliptic curves over the prime field Zp with p=192, 224 and 256, which are key sizes currently recommended by NIST. Our results show that ECC could be implemented in .Net CF with a performance that should be tolerated by most of the users with a high degree of security.

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