Publications (160) View all
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Conference Proceeding: An isolator-less CMOS RF front-end for UHF mobile RFID reader.
IEEE International Solid-State Circuits Conference, ISSCC 2011, Digest of Technical Papers, San Francisco, CA, USA, 20-24 February, 2011; 01/2011 -
Article: A 23.4 mW 68 dB Dynamic Range Low Band CMOS Hybrid Tracking Filter for ATSC Digital TV Tuner Adopting RC and Gm-C Topology.
IEEE Trans. on Circuits and Systems. 01/2011; 58-I:2346-2354. -
Article: A CMOS Active Feedback Balun-LNA With High IIP2 for Wideband Digital TV Receivers
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ABSTRACT: A wideband active feedback single-to-differential (S-to-D) low-noise amplifier (LNA) for digital TV (DTV) tuners composed of a S-to-D converter, a voltage combiner, and a negative feedback network is proposed to achieve low noise as well as to improve the linearity performances (IIP2 and IIP3) simultaneously. By feeding the single-ended output of the voltage combiner, which is used for combining the differential output of the S-to-D converter, to the input of the LNA through the feedback network, a wideband S-to-D LNA exploiting negative feedback is implemented. The differential mode operation of the voltage combiner reduces the second-order nonlinearity feedback, allowing us to improve both the IIP3 and IIP2 of the LNA at the same time. Two LNA design examples are presented to demonstrate usefulness of the proposed approach. The LNA I, by adopting a common source (CS) amplifier with a common gate, common source (CGCS) balun load as the S-to-D converter, is able to achieve a high gain and a low noise figure (NF) by increasing the loop gain. The LNA II using the differential amplifier with the ac-grounded second input terminal is designed for robust IIP2 to PVT variations.IEEE Transactions on Microwave Theory and Techniques 01/2011; · 1.85 Impact Factor -
Article: A 5.8 GHz Integrated CMOS Dedicated Short Range Communication Transceiver for the Korea/Japan Electronic Toll Collection System
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ABSTRACT: In this paper, a RF front-end of the 5.8 GHz integrated CMOS dedicated short range communication (DSRC) transceiver for the Korea/Japan electronic toll collection system is presented. The receiver uses low-IF conversion architecture for high sensitivity and low-power consumption while the transmitter uses direct up-conversion architecture for its simple structure and reliability. To solve image problem in the low-IF receiver, 10 MHz IF and 40 MHz IF are chosen for Korean and Japanese DSRC standards, respectively, since they make no image signals exist in image band. A single-quadrature mixer with the proposed transconductor-type quadrature generator in RF signal path is also adopted which has accurate quadrature characteristic in 5.8 GHz frequency. When the RF front-end of the integrated 5.8 GHz DSRC transceiver is implemented using 0.13 μm CMOS technology, the receiver achieves the overall noise figure of less than 5 dB with image rejection ratio of more than 30 dB, and the transmitter carries an output peak power of 10 dBm with the adjacent channel power ratio of -43 dBc. The RF front-end of the 5.8 GHz DSRC transceiver dissipates 45 mA with 1.2 V supply voltage and 142 mA with 1.2/3.3 V dual supply voltage during RXand TX-modes, respectively.IEEE Transactions on Microwave Theory and Techniques 12/2010; · 1.85 Impact Factor -
Article: A Low Power Broadband Differential Low Noise Amplifier Employing Noise and IM3 Distortion Cancellation for Mobile Broadcast Receivers
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ABSTRACT: A CMOS broadband differential low noise amplifier (LNA) employing noise and third order intermodulation (IM3) distortion cancellation has been designed using a 0.13 μm CMOS process for mobile TV tuners. By combining a common gate amplifier with a common source amplifier through a current mirror, a high gain due to the additional current amplification and a low noise figure (NF) due to the thermal noise cancellation can be achieved with low power consumption without degrading the input matching. To improve the linearity with low power consumption, a multiple gated transistor technique for canceling the IM3 distortion is adopted. The proposed LNA has a maximum gain of 14.5 dB, an averaged NF of 3.6 dB, an IIP3 of 3 dBm, an IIP2 of 38 dBm, and an |Sn<sub>11</sub>| lower than -9 dB in a frequency range from 72 to 850 MHz. The power consumption is 9.6 mW at a 1.2 V supply voltage and the chip area is 0.08 mm<sup>2</sup>.IEEE Microwave and Wireless Components Letters 11/2010; · 1.72 Impact Factor
