Publications (19) View all
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Conference Proceeding: High yield sub-0.1µm2 6T-SRAM cells, featuring high-k/metal-gate finfet devices, double gate patterning, a novel fin etch strategy, full-field EUV lithography and optimized junction design & layout
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ABSTRACT: We report high yield sub-0.1μm<sup>2</sup> SRAM cells using high-k/metal gate FinFET devices. Key features are (1) novel fin patterning strategy, (2) double gate patterning (3) new SRAM cell layout and (4) EUV lithography and robust etch/fill/CMP for contact/metal 1.0.099μm<sup>2</sup> FinFET 6T-SRAM cells show good yield. And smaller cells (0.089μm<sup>2</sup>) are functional. Further yield improvement is possible by junction optimization using extension less junction approach and further cell layout optimization.VLSI Technology (VLSIT), 2010 Symposium on; 07/2010 -
Conference Proceeding: Demonstration of scaled 0.099µm2 FinFET 6T-SRAM cell using full-field EUV lithography for (Sub-)22nm node single-patterning technology
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ABSTRACT: We demonstrate electrically functional 0.099 μm<sup>2</sup> 6T-SRAM cells using full-field EUV lithography for contact and M1 levels. This enables formation of dense arrays without requiring any OPC/RET, while exhibiting substantial process latitudes & potential lower cost of ownership (single-patterning). Key enablers include: 1) high-k/metal gate FinFETs with L<sub>g</sub>˜40 nm, 12-17 nm wide Fins, and cell β ratio ˜1.3; 2) option for using an extension-less approach, advantageous for reducing complexity with 2 less I/I photos, and for enabling a better quality, defect-free growth of Si-epitaxial raised S/D; 3) use of double thin-spacers and ultra-thin silicide; 4) optimized W metallization for filling high aspect-ratio, ⩾30 nm-wide contacts. SRAM cell with SNM≫10%V<sub>DD</sub> down to 0.4V, and healthy electrical characteristics for the cell transistors [SS˜80 mV/dec, DIBL˜50-80 mV/V, and |V<sub>Tlin</sub>|⩾0.2 V (PMOS), V<sub>Tlin</sub>˜0.36 V (NMOS)] are reported.Electron Devices Meeting (IEDM), 2009 IEEE International; 01/2010 -
Article: Lithography Options for the 32 nm Half Pitch Node and Beyond
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ABSTRACT: Three major technological lithography options have been reviewed for high volume manufacturing at the 32 nm half pitch node: 193 nm immersion lithography with high index materials, enabling NA > 1.6; 193 nm double patterning and EUV lithography. In this paper the evolution of these three options over 2008 is discussed. The extendibility of these options beyond 32 nm half pitch is important for the final choices to be made. During 2008, the work on high index 193 nm immersion lithography has been stopped due to lack of progress in high index optical material and high index liquid development. Double patterning has made a lot of progress but cost concerns still exist. Preferred are those resists which support pattern or image freezing techniques in order to step away from the complex litho-etch-litho-etch approach and make double patterning more cost effective. For EUV, besides the high power light source, the resist materials need to meet very aggressive sensitivity specifications and need to maintain simultaneously performance in terms of resolution and line width roughness. Furthermore, EUV reticles encounter serious challenges, primarily related to mask defectivity.Circuits and Systems I: Regular Papers, IEEE Transactions on 09/2009; · 1.97 Impact Factor -
Conference Proceeding: Status and challenges of extreme-UV lithography
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ABSTRACT: In this paper, the experiences on full field EUVL lithography are reviewed. Besides the imaging performance of the EUV ADT at IMEC, also the progress in resists and reticles are discussed and compared to the production requirements for EUV lithography.VLSI Technology, Systems, and Applications, 2009. VLSI-TSA '09. International Symposium on; 05/2009 -
Conference Proceeding: Full-field EUV and immersion lithography integration in 0.186μm2 FinFET 6T-SRAM cell
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ABSTRACT: We report on a major advancement in full-field EUV lithography technology. A single patterning approach for contact level by EUVL (NA=0.25) was used for the fabrication of electrically functional 0.186 mum<sup>2</sup> 6T-SRAMs, with W-filled contacts. Alignment to other 193 nm immersion litho levels shows very good overlay values les20 nm. Other key features of the process are: 1) use of high-k/Metal Gate FinFETs with good gate CD control: 3sigmales7 nm after double-dipole 193 nm immersion litho (NA=0.85) and 3sigmales9 nm after double-Hard Mask gate etch; and 2) use of an ultra-thin NiPt-silicide for S/D and an optimized spacers module without Si recess at dense FINs pitch. Excellent SRAM V<sub>DD</sub> scalability down to 0.6V (SNM>0.1V<sub>DD</sub>) and healthy electrical characteristics (V<sub>T</sub>, sigma(DeltaV<sub>T</sub>), I-V) for the cell transistors are obtained.Electron Devices Meeting, 2008. IEDM 2008. IEEE International; 01/2009
