Skills (40)
Research experience
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Sep 2012–
presentResearch: Research Scientist
Madrigal Elektromotoren GmbH · Chemistry · Crystallography LabUSA · Albuquerque, NMResearcher in crystallography working under renowned chemist and Caltech Alumni, W. White, Ph.D. -
Jan 2010–
Mar 2010Teaching: Teaching Assistant; Microcomputer-Based System Design (EEC 172)
University of California, Davis · Department of Electrical and Computer EngineeringUSA · Davis, CAManaged a four to five hour a week lab dealing with all aspects of embedded software development and hardware interfacing on the TI/Luminary Micro LM3S8962 microcontrollers. Graded midterms and laboratory assignments. -
Jan 2008–
May 2010Research: Laboratory Manager
University of California, Davis · Department of Electrical and Computer Engineering · VLSI Computation LaboratoryUSA · Davis, CAHandled light-weight IT support duties. Co-supervised changes in lab configuration and cubicle wall partitions. Maintained test equipment inventory and routine repairs/calibration. Gave advice on equipment and parts purchase. -
Sep 2007–
Oct 2007Research: Chip Packaging and Hardware Test Engineer
University of California, Davis · Department of Electrical and Computer Engineering · VLSI Computation LaboratoryUSA · Davis, CASelected the appropriate packages for short-term prototyping and long-term testing of a 300+ pin chip. Designed the PCB layout for a custom interface board between configuration FPGA and chip for short-term prototyping. -
Sep 2006–
Jun 2007Research: Manycore Platform Lead Architect
University of California, Davis · Department of Electrical and Computer Engineering · VLSI Computation LaboratoryUSA · Davis, CAWorked with a team of 10 M.S. and Ph.D. students on a 167-core GALS array consisting of 164 DSP processors, three accelerators, and three scratchpad memories. Design to tape-out took 9 months on 65 nm CMOS. -
Jun 2005–
Sep 2012Research: Research Assistant
University of California, Davis · Department of Electrical and Computer Engineering · VLSI Computation LaboratoryUSA · Davis, CAAcquired chip measurements of a 36-core DSP GALS platform, and a 167-core platform with DVFS. Worked on control theoretic modeling of per-core DVFS in Simulink. Published 16 authored and co-authored works in IEEE/ACM conferences and journals.
Education
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Sep 2005–
Jan 2013University of California at Davis
Electrical and Computer Engineering · Ph.D.USA · Davis, CA -
Sep 2005–
May 2010University of California at Davis
Eletrical and Computer Engineering · M.S.USA · Davis, CA -
Sep 2001–
Jul 2005University of California at Davis
Electrical and Computer Engineering · B.S.USA · Davis, CA
Awards & achievements
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Dec 2010Award: Graduate Student Travel Award (USD$1000.00)
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Apr 2009Grant: Block Grant Fellowship (USD$955.87)
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Sep 2006Scholarship: Graduate Assistance in Areas of National Need (GAANN) Fellowship (USD$23622.16)
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Jan 2006Scholarship: UC Microelectronics Innovation and Computer Research Opportunities (MICRO) Fellowship (USD$14359.00)
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Sep 2005Grant: Block Grant Fellowship (USD$6186.50)
Other
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LanguagesEnglish! (American Variant)
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Scientific MembershipsIEEE, SRC, ACM
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Journal Referees+ 48th ACM/IEEE Design Automation Conference, + 2012 and 2013 IEEE International Symposium on Circuits and Systems, IEEE Journal of Solid-State Circuits, IEEE Design and Test of Computers, IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing, Recent Patents on Electrical Engineering, Bentham Science Publishers
Publications (23) View all
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Conference Proceeding: Massively Parallel Processor Array for Mid-/Back-end Ultrasound Signal Processing
11/2010 -
Conference Proceeding: Circuit modeling for practical many-core architecture design exploration
06/2010 -
Article: A Low-Complexity Message-Passing Algorithm for Reduced Routing Congestion in LDPC Decoders
[show abstract] [hide abstract]
ABSTRACT: A low-complexity message-passing algorithm, called Split-Row Threshold, is used to implement low-density parity-check (LDPC) decoders with reduced layout routing congestion. Five LDPC decoders that are compatible with the 10GBASE-T standard are implemented using MinSum Normalized and MinSum Split-Row Threshold algorithms. All decoders are built using a standard cell design flow and include all steps through the generation of GDS II layout. An Spn = 16 decoder achieves improvements in area, throughput, and energy efficiency of 4.1 times, 3.3 times, and 4.8 times, respectively, compared to a MinSum Normalized implementation. Postlayout results show that a fully parallel Spn = 16 decoder in 65-nm CMOS operates at 195 MHz at 1.3 V with an average throughput of 92.8 Gbits/s with early termination enabled. Low-power operation at 0.7 V gives a worst case throughput of 6.5 Gbits/s-just above the 10GBASE-T requirement-and an estimated average power of 62 mW, resulting in 9.5 pj/bit. At 0.7 V with early termination enabled, the throughput is 16.6 Gbits/s, and the energy is 3.7 pJ/bit, which is 5.8?? lower than the previously reported lowest energy per bit. The decoder area is 4.84 mm2 with a final postlayout area utilization of 97%.Circuits and Systems I: Regular Papers, IEEE Transactions on 05/2010; 57:1048 -1061. · 1.97 Impact Factor -
Conference Proceeding: Circuit modeling for practical many-core architecture design exploration.
Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010; 01/2010 -
Conference Proceeding: An Improved Split-Row Threshold Decoding Algorithm for LDPC Codes
[show abstract] [hide abstract]
ABSTRACT: We present an improved thresholding LDPC decoding algorithm which outperforms the split-row and original split-row threshold decoders with a small increase in hardware. Simulation results show that the algorithm provides 0.27- 0.50 dB coding gain over split-row, 0.10-0.20 dB over split-row threshold, and is within 0.08-0.13 dB of SPA. Compared with the original threshold algorithm the check node processor's gate count is increased by 3% while total chip area is kept the same.Communications, 2009. ICC '09. IEEE International Conference on; 07/2009
