Dean Truong

Publications

• Massively Parallel Processor Array for Mid-/Back-end Ultrasound Signal Processing

  D.N. Truong, B.M. Baas

  11/2010

• Circuit modeling for practical many-core architecture design exploration

  D.N. Truong, B.M. Baas

  06/2010

• A Reconfigurable Source-Synchronous On-Chip Network for GALS Many-Core Platforms

  Anh Thien Tran, Dean Nguyen Truong, B. Baas

  Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on. 06/2010; 29:897 -910.

• A Low-Complexity Message-Passing Algorithm for Reduced Routing Congestion in LDPC Decoders

  T. Mohsenin, D.N. Truong, B.M. Baas

  Circuits and Systems I: Regular Papers, IEEE Transactions on. 05/2010; 57:1048 -1061.

• An Improved Split-Row Threshold Decoding Algorithm for LDPC Codes

  T. Mohsenin, D. Truong, B. Baas

  Communications, 2009. ICC '09. IEEE International Conference on; 07/2009

  We present an improved thresholding LDPC decoding algorithm which outperforms the split-row and original split-row threshold decoders with a small increase in hardware. Simulation results show that the algorithm provides 0.27- 0.50 dB coding gain over split-row, 0.10-0.20 dB over split-row threshold... [more] We present an improved thresholding LDPC decoding algorithm which outperforms the split-row and original split-row threshold decoders with a small increase in hardware. Simulation results show that the algorithm provides 0.27- 0.50 dB coding gain over split-row, 0.10-0.20 dB over split-row threshold, and is within 0.08-0.13 dB of SPA. Compared with the original threshold algorithm the check node processor's gate count is increased by 3% while total chip area is kept the same.

• Multi-Split-Row Threshold decoding implementations for LDPC codes

  T. Mohsenin, D. Truong, B. Baas

  Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on; 06/2009

  The recently introduced Split-Row Threshold algorithm significantly improves the error performance when compared to the non- threshold Split-Row algorithm while requiring a very small increase in hardware complexity. The Multi-Split-Row Threshold decoding algorithm presented in this paper enables fu... [more] The recently introduced Split-Row Threshold algorithm significantly improves the error performance when compared to the non- threshold Split-Row algorithm while requiring a very small increase in hardware complexity. The Multi-Split-Row Threshold decoding algorithm presented in this paper enables further reductions in routing complexity for greater throughput and smaller circuit area implementations. Several Multi-Split-Row Threshold decoder designs have been implemented in 65 nm CMOS and the impact of the different levels of partitioning on error performance, wire interconnect complexity, decoder area, and speed are investigated. The Split-Row-16 Threshold decoder occupies 3.8 mm², runs at 100 MHz, delivers a throughput of 13.8 Gbps at 15 iterations and is only 0.28 dB and 0.22 dB away from SPA and MinSum Normalized.

• An Improved Split-Row Threshold Decoding Algorithm for LDPC Codes

  T. Mohsenin, D. Truong, B. Baas

  06/2009

• Multi-Split-Row Threshold decoding implementations for LDPC codes

  T. Mohsenin, D. Truong, B. Baas

  05/2009

• The design of a reconfigurable continuous-flow mixed-radix FFT processor

  A.T. Jacobson, D.N. Truong, B.M. Baas

  05/2009

• A low-cost high-speed source-synchronous interconnection technique for GALS chip multiprocessors

  A.T. Tran, D.N. Truong, B.M. Baas

  05/2009

• A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network

  A.T. Tran, D.N. Truong, B.M. Baas

  05/2009

• A 167-Processor Computational Platform in 65 nm CMOS

  D.N. Truong, W.H. Cheng, T. Mohsenin, Zhiyi Yu, A.T. Jacobson, G. Landge, M.J. Meeuwsen, C. Watnik, A.T. Tran, Zhibin Xiao, E.W. Work, J.W. Webb, P.V. Mejia, B.M. Baas

  Solid-State Circuits, IEEE Journal of. 04/2009; 44:1130 -1144.

• A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network.

  Anh Thien Tran, Dean Truong, Bevan M. Baas

  Third International Symposium on Networks-on-Chips, NOCS 2009, May 10-13 2009, La Jolla, CA, USA. Proceedings; 01/2009

• A complete real-time 802.11a baseband receiver implemented on an array of programmable processors

  A.T. Tran, D.N. Truong, B.M. Baas

  10/2008

• A 167-processor Computational Array for Highly-Efficient DSP and Embedded Application Processing

  Dean Truong, Wayne Cheng, Tinoosh Mohsenin, Zhiyi Yu Toney Jacobson, Gouri Landge, Michael Meeuwsen, Christine Watnik, Paul Mejia, Anh Tran, Jeremy Webb, Eric Work, Zhibin Xiao, Bevan Baas

  08/2008

• Hardware and Applications of AsAP: An Asynchronous Array of Simple Processors

  Dean Truong, Wayne Cheng, Tinoosh Mohsenin, Zhiyi Yu Toney Jacobson, Gouri Landge, Michael Meeuwsen, Christine Watnik, Paul Mejia, Anh Tran, Jeremy Webb, Eric Work, Zhibin Xiao, Bevan Baas

  08/2008

• A 167-processor 65 nm computational platform with per-processor dynamic supply voltage and dynamic clock frequency scaling

  D. Truong, W. Cheng, T. Mohsenin, Zhiyi Yu, T. Jacobson, G. Landge, M. Meeuwsen, C. Watnik, P. Mejia, Anh Tran, J. Webb, E. Work, Zhibin Xiao, B. Baas

  VLSI Circuits, 2008 IEEE Symposium on; 07/2008

  A 167-processor 65 nm computational platform well suited for DSP, communication, and multimedia workloads contains 164 programmable processors with dynamic supply voltage and dynamic clock frequency circuits, three algorithm-specific processors, and three 16 KB shared memories, all clocked by indepe... [more] A 167-processor 65 nm computational platform well suited for DSP, communication, and multimedia workloads contains 164 programmable processors with dynamic supply voltage and dynamic clock frequency circuits, three algorithm-specific processors, and three 16 KB shared memories, all clocked by independent oscillators and connected by configurable long-distance-capable links.
• 3.15

  Impact points

  AsAP: An Asynchronous Array of Simple Processors

  Zhiyi Yu, M.J. Meeuwsen, R.W. Apperson, O. Sattari, M. Lai, J.W. Webb, E.W. Work, D. Truong, T. Mohsenin, B.M. Baas

  Solid-State Circuits, IEEE Journal of. 04/2008;

  An array of simple programmable processors is implemented in 0.18 mum CMOS and contains 36 asynchronously clocked independent processors. Each processor occupies 0.66 and is fully functional at a clock rate of 520-540 MHz at 1.8 V and over 600 MHz at 2.0 V. Processors dissipate an average of 32 mW u... [more] An array of simple programmable processors is implemented in 0.18 mum CMOS and contains 36 asynchronously clocked independent processors. Each processor occupies 0.66 and is fully functional at a clock rate of 520-540 MHz at 1.8 V and over 600 MHz at 2.0 V. Processors dissipate an average of 32 mW under typical conditions at 1.8 V and 475 MHz, and 2.4 mW at 0.9 V and 116 MHz while executing applications such as a JPEG encoder core and a fully compliant IEEE 802.11 a/g wireless LAN baseband transmitter.
• 3.21

  Impact points

  AsAP: A Fine-Grained Many-Core Platform for DSP Applications

  B. Baas, Zhiyi Yu, M. Meeuwsen, O. Sattari, R. Apperson, E. Work, J. Webb, M. Lai, T. Mohsenin, D. Truong, J. Cheung

  Micro, IEEE. 04/2007;

  Many emerging and future applications require significant levels of complex digital signal processing and operate within limited power budgets. Moreover, dramatically rising VLSI fabrication and design costs make programmable and reconfigurable solutions increasingly attractive. the ASAP project add... [more] Many emerging and future applications require significant levels of complex digital signal processing and operate within limited power budgets. Moreover, dramatically rising VLSI fabrication and design costs make programmable and reconfigurable solutions increasingly attractive. the ASAP project addresses these challenges with a chip multiprocessor composed of simple processors with small memories, achieving high energy efficiency and throughput in a small chip area.