Daniel M. Dreps

Publications (9) View all

• Article: Packaging design challenges of the IBM System z10 Enterprise Class server

  T.-M. Winkel, H. Harrer, D. Kaller, J. Supper, D. M. Dreps, K. L. Christian, D. Cosmadelis, T. Zhou, T. Strach, J. Ludwig, D. L. Edwards
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  ABSTRACT: This paper describes the system packaging and technologies of the IBM System z10™ high-end Enterprise Class server. This machine exceeds the multiprocessor performance of the previous system by 50%. A new generation of the IBM Elastic Interface was developed in order to maintain the increased interconnect signal speed of up to 2.93 Gb/s. Power control and power delivery to the multicore processors were a special challenge for the server packaging because of the high currents and the high number of voltage domains.
  Ibm Journal of Research and Development 02/2009; · 0.72 Impact Factor
• Source

  Available from: Alina Deutsch

  Conference Proceeding: Design methodology of high performance on-chip global interconnect using terminated transmission-line.

  Yulei Zhang, Ling Zhang, Alina Deutsch, George A. Katopis, Daniel M. Dreps, James F. Buckwalter, Ernest S. Kuh, Chung-Kuan Cheng
  10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA; 01/2009
• Conference Proceeding: A 5.4mW 0.0035mm

  Kyu-hyoun Kim, Daniel M. Dreps, Frank D. Ferraiolo, Paul W. Coteus, Seongwon Kim, Sergey V. Rylov, Daniel J. Friedman
  IEEE International Solid-State Circuits Conference, ISSCC 2009, Digest of Technical Papers, San Francisco, CA, USA, 8-12 February, 2009; 01/2009
• Article: Packaging design challenges of the IBM System z10 Enterprise Class server.

  Thomas-Michael Winkel, Hubert Harrer, Dierk Kaller, Jochen Supper, Daniel M. Dreps, Kenneth L. Christian, D. Cosmadelis, Tingdong Zhou, Thomas Strach, J. Ludwig, David L. Edwards
  IBM Journal of Research and Development. 01/2009; 53:10.
• Source

  Available from: Wenjian Yu

  Conference Proceeding: Low Power Passive Equalizer Design for Computer Memory Links

  Ling Zhang, Wenjian Yu, Yulei Zhang, Renshen Wang, Alina Deutsch, George A. Katopis, Daniel M. Dreps, James Buckwalter, Ernest Kuh, Chung-Kuan Cheng
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  ABSTRACT: Several types of low power passive equalizer is proposed and optimized in this work. The equalizer topologies include T-junction, parallel R-C and series R-L structures. These structures can be inserted at driver or/and receiver side at either the chip or package level and the communication bandwidth can be improved with little overhead on power consumption. Using the area of the eye as the objective function to be maximized, we optimized these equalizers for the CPU-memory interconnection of an IBM POWER6 System with and without practical constraints on the RLCG parameter values. Our experimental results show that without employing any equalizers, the data-eye is closed for a bit-rate of 6.4 Gbps. We tried twelve different equalizer schemes and found they produce very different eye diagrams. The scheme yielding the maximum eye improves the height of the eye to more than 300 mV at a total power cost of 7.2 mW, while the scheme yielding the minimum jitter limits the jitter magnitude to 10 ps at a total power cost of 9.5 mW. We also have shown that the solution resulting from the proposed optimization approach have very small sensitivity to the tolerance of the R,L,C values and the magnitude of the coupled noise.
  High Performance Interconnects, 2008. HOTI '08. 16th IEEE Symposium on; 09/2008