Ayoub Khan
Research skills
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TechnicalSimulation Modelsim XE III, Cadence NC-Verilog, Timing Analysis STA, trace, Xilinx PACE, Chipscope Pro, ISE Architecture Wizard, Synthesis XST, Leonardo Spectrum LS2004a, Devices Xilinx Spartan-II, III, Vertex-II, Implementation Xilinx ISE 6.3i, Xilinx iMPACT, Xilinx coregen, Embedded Systems Intel 8086 family, Intel 8085 family, and Motorola 68HC11 family., HDLs: Verilog, Software Language: C, C++, assembly language, 8086 /8051, MatLab 6.5, Operating System UNIX shell programming, Sun Solaris 5.8, RTOS-VxWorks, Design Methodologies OOA/OOD methodologies including UML using Rational Rose, Ptolemy II 4.0
Research interests
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InterestsVLSI ( Digital System, Network-on-Chip, Routing, switch design, low power), Embedded System, Radio Frequency, NFC, System on Chip Design
Research experience
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Teaching: RTL Design Verilog
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Teaching: Synthesis
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Teaching: Parallel Processing
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Teaching: Algorithm for VLSI Design automation
Education
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Jan 2008
Jamia Millia Islamia
Area efficient routing in 3-D Network-on-Chip · Ph.d( Electrical Engg)India · New Delhi
Other
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LanguagesEnglish, Urdu, Arabic, Hindi
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Scientific MembershipsIEEE,ISTE, ACEEE, IACSIT, IAENG
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Journal RefereeIEEE Transaction on Industrial Informatics, IEEE Communication Letters, Elsevier Journal of Network and Computer Applications
Following (9)
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Hashim Ali
Università degli Studi di Milano-Bicocca -
Nora Konopka
CRC Press Online -
Syed Manzoor Qasim
King Abdulaziz City for Science and Technology -
Sanja Lazarova-Molnar
United Arab Emirates University -
Xun Zhang
IEEE