Publications (85) View all
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Chapter: An AER Spike-Processing Filter Simulator and Automatic VHDL Generator Based on Cellular Automata
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ABSTRACT: Spike-based systems are neuro-inspired circuits implementations traditionally used for sensory systems or sensor signal processing. Address-Event-Representation (AER) is a neuromorphic communication protocol for transferring asynchronous events between VLSI spike-based chips. These neuro-inspired implementations allow developing complex, multilayer, multichip neuromorphic systems and have been used to design sensor chips, such as retinas and cochlea, processing chips, e.g. filters, and learning chips. Furthermore, Cellular Automata (CA) is a bio-inspired processing model for problem solving. This approach divides the processing synchronous cells which change their states at the same time in order to get the solution. This paper presents a software simulator able to gather several spike-based elements into the same workspace in order to test a CA architecture based on AER before a hardware implementation. Furthermore this simulator produces VHDL for testing the AER-CA into the FPGA of the USB-AER AER-tool. Keywordsspiking neurons–address-event-representation–usb-aer–vhdl–fpga–image filtering–neuro-inspired–cellular automata05/2011: pages 157-165; -
Chapter: Visual Spike Processing based on Cellular Automaton
04/2011; , ISBN: 978-953-307-230-2 -
Conference Proceeding: Visual spike-based convolution processing with a Cellular Automata architecture
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ABSTRACT: This paper presents a first approach for implementations which fuse the Address-Event-Representation (AER) processing with the Cellular Automata using FPGA and AER-tools. This new strategy applies spike-based convolution filters inspired by Cellular Automata for AER vision processing. Spike-based systems are neuro-inspired circuits implementations traditionally used for sensory systems or sensor signal processing. AER is a neuromorphic communication protocol for transferring asynchronous events between VLSI spike-based chips. These neuro-inspired implementations allow developing complex, multilayer, multichip neuromorphic systems and have been used to design sensor chips, such as retinas and cochlea, processing chips, e.g. filters, and learning chips. Furthermore, Cellular Automata is a bio-inspired processing model for problem solving. This approach divides the processing synchronous cells which change their states at the same time in order to get the solution.Neural Networks (IJCNN), The 2010 International Joint Conference on; 08/2010 -
Conference Proceeding: Determination of a power-saving method for real-time wireless sensor networks
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ABSTRACT: In wireless sensor networks, battery life is a key resource that must be conserved as much as possible. Nowadays, the main way of achieve power saving in this type of circuits is to implement low-power RF (Radio Frequency) circuitry and network protocols that try to minimize the number of transmissions by the air. We think that adaptation to RF environment can minimize the power consumption and supply an extra saving of energy in this type of systems. This paper presents a power-saving method for wireless sensor networks with real-time constrains. Description of an example of this type of systems will be done in order to supply background where needs and challenges will be presented. Then, method will be presented with some results in order to obtain conclusions and an estimation of future works and applications.Performance Evaluation of Computer and Telecommunication Systems (SPECTS), 2010 International Symposium on; 08/2010 -
Chapter: FPGA Implementations Comparison of Neuro-cortical Inspired Convolution Processors for Spiking Systems
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ABSTRACT: Image convolution operations in digital computer systems are usually very expensive operations in terms of resource consumption (processor resources and processing time) for an efficient Real-Time application. In these scenarios the visual information is divided in frames and each one has to be completely processed before the next frame arrives. Recently a new method for computing convolutions based on the neuro-inspired philosophy of spiking systems (Address-Event-Representation systems, AER) is achieving high performances. In this paper we present two FPGA implementations of AER-based convolution processors that are able to work with 64x64 images and programmable kernels of up to 11x11 elements. The main difference is the use of RAM for integrators in one solution and the absence of integrators in the second solution that is based on mapping operations. The maximum equivalent operation rate is 163.51 MOPS for 11x11 kernels, in a Xilinx Spartan 3 400 FPGA with a 50MHz clock. Formulations, hardware architecture, operation examples and performance comparison with frame-based convolution processors are presented and discussed.06/2009: pages 97-105;
