Publications (60) View all
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Conference Proceeding: Ultra-dense monolithic integration of optical and electrical functions on silicon for optical interconnects
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ABSTRACT: CMOS Integrated Nanophotonics which allows dense monolithic integration of optical and electrical functions on the same chip can enable future Exaflops supercomputers by connecting racks, modules, and chips together with ultra-low power massively parallel optical interconnects.General Assembly and Scientific Symposium, 2011 XXXth URSI; 09/2011 -
Conference Proceeding: A 3.9ns 8.9mW 4×4 silicon photonic switch hybrid integrated with CMOS driver
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ABSTRACT: The emerging field of silicon photonics targets monolithic integration of optical components in the CMOS process, potentially enabling high bandwidth, high density interconnects with dramatically reduced cost and power dissipation. A broadband photonic switch is a key component of reconfigurable networks which retain data in the optical domain, thus bypassing the latency, bandwidth and power overheads of opto-electronic conversion. Additionally, with WDM channels, multiple data streams can be routed simultaneously using a single optical device. Although many types of discrete silicon photonic switches have been reported, very few of them have been shown to operate with CMOS drivers. Earlier, we have reported two different 2×2 optical switches wirebond packaged with 90nm CMOS drivers. The 2×2 switch reported in is based on a Mach-Zehnder interferometer (MZI), while the one reported in is based on a two-ring resonator.Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011 IEEE International; 03/2011 -
Conference Proceeding: A compact 6 GHz to 12 GHz digital PLL with coupled dual-LC tank DCO
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ABSTRACT: A digital PLL, realized in 45nm SOI CMOS, features a dual LC-tank DCO with nested inductors, achieving an octave of tuning range and area of 0.111 mm<sup>2</sup>. Digital control of coupled LC-tanks creates new capabilities, enabling a 10% increase in tuning range and a 28 times reduction of DCO gain. The rms jitter, integrated from fc/1667 to fc/2, is 362 fs at 12 GHz and 274 fs at 6 GHz.VLSI Circuits (VLSIC), 2010 IEEE Symposium on; 07/2010 -
Conference Proceeding: A DPLL-based per core variable frequency clock generator for an eight-core POWER7™ microprocessor
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ABSTRACT: A per-core clock generator for the eight-core POWER7<sup>™</sup> processor is implemented with a digital PLL. This frequency generator is capable of smooth, controlled frequency slewing, minimizing the impact of di/dt. Frequency can be dynamically adjusted while the clock is running, and without skipping any cycles, thus enabling aggressive power management techniques.VLSI Circuits (VLSIC), 2010 IEEE Symposium on; 07/2010 -
Conference Proceeding: Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications
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ABSTRACT: This paper describes an integer-N BB-PFD DPLL architecture for wireline communication applications. The feasibility of the structure is demonstrated by implementations targeting applications in the 8-to-11 Gb/s and 17-to-20 Gb/s ranges. A key challenge associated with this approach is how to achieve the proportional-path latency and gain required for overall low-noise DPLL performance. In particular, it is well-known that the strong nonlinearity introduced by the BB-PFD manifests itself as a bounded limit cycle. This results in the DPLL output jitter to increase as the proportional path latency and gain increase. To minimize the negative effect of the limit cycle, the DPLL architecture features a separate low-latency proportional path, with the BB- PFD output directly controlling the DCO. Other features include controllability of the proportional-path gain and of the BBPFD gain.Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International; 03/2009
