IEEE Circuits and Devices Magazine (IEEE Circ Dev Mag)

Publisher: Institute of Electrical and Electronics Engineers, Institute of Electrical and Electronics Engineers

Journal description

This professional magazine contains information on electronic and photonic technologies presented in a lucid manner. Authoritative feature articles cover the design, implementation, packaging, and manufacture of micro-electronic and photonic devices, circuits and systems. Columns address news and issues of practical concern in all areas covered by the magazine. Conference and society coverage, reviews of new books, products and software help keep readers up to date. C & D Magazine is useful for practicing engineers, managers, students, and research engineers desiring to keep abreast of the latest technology developments. C & D Magazine covers the technical interests of CAS, ED, and LEO.

Current impact factor: 1.18

Impact Factor Rankings

2015 Impact Factor Available summer 2015
2008 Impact Factor 1.741
2007 Impact Factor 1.184
2006 Impact Factor 1.22
2005 Impact Factor 0.745
2004 Impact Factor 1.115
2003 Impact Factor 0.955
2002 Impact Factor 1.171
2001 Impact Factor 1.147
2000 Impact Factor 0.327
1999 Impact Factor 0.42
1998 Impact Factor 0.25
1997 Impact Factor 0.244

Impact factor over time

Impact factor

Additional details

5-year impact 0.00
Cited half-life 5.90
Immediacy index 0.00
Eigenfactor 0.00
Article influence 0.00
Website IEEE Circuits and Devices Magazine website
Other titles IEEE circuits and devices magazine., IEEE circuits and devices magazine, Institute of Electrical and Electronics Engineers circuits and devices, IEEE circuits and devices, Circuits & devices, Circuits and devices
ISSN 8755-3996
OCLC 25673740
Material type Periodical, Internet resource
Document type Journal / Magazine / Newspaper, Internet Resource

Publisher details

Institute of Electrical and Electronics Engineers

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  • Classification
    ‚Äč green

Publications in this journal

  • [Show abstract] [Hide abstract]
    ABSTRACT: The random jitter performance of clock, oscillator, and timing circuits can be predicted by using steady-state circuit simulation techniques that determine phase noise by analyzing the impact on phase due to thermal, flicker, channel, and shot noise present in the electronic devices. Given the phase noise response, and the steady-state operating conditions of the circuit, a wide variety of jitter measurements can be computed. Each involves a transformation of the phase noise results, with accuracy hinging on the quality of the phase noise response over a suitable range of offset frequencies
    IEEE Circuits and Devices Magazine 12/2006; DOI:10.1109/MCD.2006.307274
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    ABSTRACT: This article has provided a brief overview of the SigmaDelta ADC conversion technologies for SDRs. The wireless receiver challenges were identified, the ADC design considerations and SigmaDelta solutions were discussed, and a low-distortion CT BP SigmaDelta modulator architecture was presented. The article has shown that the proposed CT BP SigmaDelta modulator is suitable for implementing high-IF ADC, making possible the software radio in handhelds. The major challenges in implementing such a high-IF ADC are the power dissipation and the degree of configurability, programmability, and adaptability that can be achieved by applying digital tuning and adaptive calibration
    IEEE Circuits and Devices Magazine 12/2006; DOI:10.1109/MCD.2006.307273
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    ABSTRACT: Current integration trends imposed by the market are pushing toward the software radio paradigm. 4G radio receivers, where different wireless standards converge, make RF engineers face harder and harder challenges. Electronic design automation (EDA) tools play an increasing role in the design and verification of wireless system. This article presents a transceiver architecture comparison tool (TACT) which is a hierarchical, user-friendly, Matlab-based tool. It automates the design-space exploration procedure for 4G (fourth generation) wireless receivers. An example that considers a multistandard wideband code division multiple access (WCDMA)/wireless local area network (WLAN) receiver was also presented to illustrate the capabilities of TACT
    IEEE Circuits and Devices Magazine 12/2006; DOI:10.1109/MCD.2006.307272
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    ABSTRACT: A 2-kb embedded EEPROM memory, operating over a wide voltage range (typically 2.5 V-5 V), was designed and fabricated using the SMIC 0.35-mum 2P3M CMOS embedded EEPROM process. The chip size is about 0.6 mm<sup>2</sup>. The method of adding control transistors improved the static power dissipation. The transient power consumption of the charge pump circuit was greatly reduced by using a slowly varying clock. The proposed SA using a voltage sensing method also significantly improved the read power dissipation. By employing these techniques, a low-power embedded EEPROM memory with 40 muA read current and 250 muA page write current was developed, that achieved much lower power than EEPROM memory designs reported in scientific journals or conferences. This EEPROM memory was used in the ISO/IEC 15693-compatible RFID tag IC project
    IEEE Circuits and Devices Magazine 12/2006; DOI:10.1109/MCD.2006.307277
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    ABSTRACT: A new class of unique linear and angular nanopositioners has been developed based on the novel properties of an advanced rotary piezoelectric motor. These new devices substantially improve positioning performance and open new possibilities for biomedical research studies
    IEEE Circuits and Devices Magazine 12/2006; 22(6):75-78. DOI:10.1109/MCD.2006.307280
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    ABSTRACT: The super junction (SJ) concept (Coe et al.) applied to power semiconductor devices is attractive due to its potential for reducing on-resistance at a given breakdown voltage. Discrete SJ vertical power devices have recently become available commercially. However, lateral SJ devices have not materialized for several years partly due to the fact that the lateral SJ structure, implemented on silicon substrates, suffers from substrate-assisted depletion effects which reduce the breakdown voltage. This article discusses the various device structures that have been proposed to eliminate the substrate-assisted depletion effects in SJ-lateral double diffused MOS LDMOS transistors (SJ-LDMOSTs). The concept of the SJ device and vertical and lateral SJ structure was summarized. The substrate-assisted depletion effects are described in detail. The alternative implementations proposed to suppress the substrate effects were then discussed. And the experimental implementation results are summarized and discussed to identify the most likely option for the implementation of lateral SJ-LDMOSTs
    IEEE Circuits and Devices Magazine 12/2006; DOI:10.1109/MCD.2006.307271
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    ABSTRACT: This article has presented for the first time a scientific and mathematically sound principle that enables both analog and discrete subsystems to be represented uniformly within a single framework, thereby facilitating their simultaneous and uniform simulation within the same simulator. While the combination of the laboratory prototype analog subsystem simulator, DiamSim, and available discrete-event simulators such as VHDL constitute necessary and sufficient proof of the principle, the article outlines how a unified language and execution environment, nVHDL, may be realized for the future. In the coming age of networked computational systems (NCS), future complex systems will include analog hardware, synchronous and asynchronous discrete hardware, software, and inherently asynchronous networks that will interconnect both stationary and mobile entities, all governed by asynchronous control and coordination algorithms (Ghosh,2006). Paul (2006) believes that the current object-oriented programming is being quickly obsoleted by the increasing demands of net-centric warfare and that a dynamic, service-oriented architecture is critically needed to address key future needs of the US DoD. Logic dictates that nVHDL will likely play a key role in the development of a whole new approach, networked computational systems design language and execution environment (NCSDL). that will consist of a language in which complex systems may be described accurately and an execution environment that will permit the realistic execution of the executable description on a testbed to assess the system correctness, reliability, safety, security, and other performance parameters. Furthermore, to obtain results quickly for large systems and use them in iterating system designs, the testbed must consist of a network of workstations configured as a loosely-coupled parallel processor
    IEEE Circuits and Devices Magazine 12/2006; DOI:10.1109/MCD.2006.307276
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    ABSTRACT: Not Available
    IEEE Circuits and Devices Magazine 12/2006; 22(6):2-2. DOI:10.1109/MCD.2006.307268
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    ABSTRACT: The main goal of this study is to develop novel fiber-optic-based nanobiophotonics techniques for noninvasive imaging and biosensing optical properties of cellular and tissue samples beyond the diffraction barrier in the subwavelength nanoscale range. The work covers fundamental principles, recent developments, and trends in advanced nanobiophotonics techniques exploited for either minimally invasive diagnostics and imaging in biomedicine at cellular/intracellular level or development of nanosensors and nanostructured materials. Somerecently developed advanced ultrahigh-resolution nanotechnologies such as confocal nanoscopy and fiber-optic-based nanosensors, will also be discussed. These technologies allow one to break the theoretical optical diffraction barrier and to work in the subwavelength nanoscale range
    IEEE Circuits and Devices Magazine 12/2006; 22(6):60-65. DOI:10.1109/MCD.2006.307278
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    ABSTRACT: The following books are reviewed: Digital Logic and Microcomputer Design, 5th Ed. (Rafiquzzaman, M.; 2005); Engineering Thin Films and Nanostructures with Ion Beams (Knystautas, E., Ed.); Advanced Electronic Packaging, 2nd Ed. (Ulrich, R.N. and Brown, W.D.; 2006); Passive Micro-Optical Alignment Methods (Boudreau, R.A. and Boudreau, S.M., Eds.; 2005); Fundamentals of Wireless Communication (Tse, D. And Viswanath, P.; 2005); Theory of Remote Image Formation (Blahut, R.E.; 2005); Synthesis of Arithmetic Circuits (Deschamps, J. et al.; 2006); Semiconductor Material and Device Characterization (Schroder, D.K.; 2006); Design of Interconnection Networks for Programmable Logic (Lemieux, G. and Lewis, D.; 2003); Noise in High-Frequency Circuits and Oscillators (Schiek, B. et al.; 2006); Fiber to the Home: The New Empowerment (Green, P.E., Jr.; 2005); Fundamentals of Semiconductor Manufacturing and Process Control (May, G.S. and Spanos, C.J.; 2006); WCDMA Design Handbook (Richardson, A.; 2005); Phaselock Techniques, 3rd Ed. (Gardner, F.M.; 2005); Microwave Devices, Circuits and Subsystems (Glover, I.A. et al., Eds.; 2005); Modern Microwave and Millimeter-Wave Power Electronics (Barker, R.J. et al.; 2005); Fundamentals of Telecommunications, 2nd Ed. (Freeman, R.L.; 2005); Designing Digital Computer Systems with Verilog (Lilja, D.J. and Sapatnekar, S.S.; 2005).
    IEEE Circuits and Devices Magazine 12/2006; 22(6):87-92. DOI:10.1109/MCD.2006.307282
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    ABSTRACT: Not Available
    IEEE Circuits and Devices Magazine 12/2006; 22(6):3-5. DOI:10.1109/MCD.2006.307269
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    ABSTRACT: Research is underway to explore the feasibility of implementing complete RF subsystems in standard mainstream CMOS processes without a need for any off-chip components. Progress to date has verified that RF circuits and on-chip antennas adequate for chip to chip communication can be realized, and it can be stated with some certainty that feasibility has been established. Radio architecture, signaling methodology, and individual circuit blocks have been devised and confirmed. It remains to demonstrate an on-chip reference with +/-150 ppm stability, optimize the individual circuit blocks, and demonstrate the overall concept in a single integrated chip
    IEEE Circuits and Devices Magazine 12/2006; DOI:10.1109/MCD.2006.307275
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    ABSTRACT: Peak detectors (or envelope detectors) are commonly found in modern communication receivers mainly as a building block of automatic gain control (AGC) loops. The main function of the peak detectors is to detect the peak value of an input signal and track the peak over time. In this paper, some of peak detector topologies and their applications in multistandard wireless receivers was presented
    IEEE Circuits and Devices Magazine 12/2006; 22(6-22):6 - 9. DOI:10.1109/MCD.2006.307270
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    ABSTRACT: Not Available
    IEEE Circuits and Devices Magazine 12/2006; 22(6):105-105. DOI:10.1109/MCD.2006.307286
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    ABSTRACT: The development trend in compact modeling goes toward surface-potential-based approaches and leads to models like HiSIM2, with higher accuracy, fewer model parameters, and shorter computer runtime than achievable with the conventional threshold-voltage-based approaches. The main motivation for continuing this development effort is to realize a sufficient design capability of RF circuits with advanced MOSFETs, where many higher-order phenomena affect the circuit performance, as well as of large mixed-signal circuits, where both accuracy and short simulation time are a must. The trend toward the surface potential brings compact modeling for circuit simulation also much closer to 2D and three-dimensional numerical device simulation. Therefore, both approaches can now come together and work united to achieve the common goal of realizing rapid technology progress for the benefit of the society
    IEEE Circuits and Devices Magazine 10/2006; DOI:10.1109/MCD.2006.272998