Journal of Real-Time Image Processing

Publisher: Springer Verlag

Description

  • Impact factor
    1.16
  • 5-year impact
    1.06
  • Cited half-life
    3.70
  • Immediacy index
    0.10
  • Eigenfactor
    0.00
  • Article influence
    0.43
  • Other titles
    Real-time image processing
  • ISSN
    1861-8200
  • OCLC
    73532162
  • Material type
    Document, Periodical, Internet resource
  • Document type
    Internet Resource, Computer File, Journal / Magazine / Newspaper

Publisher details

Springer Verlag

  • Pre-print
    • Author can archive a pre-print version
  • Post-print
    • Author can archive a post-print version
  • Conditions
    • Authors own final version only can be archived
    • Publisher's version/PDF cannot be used
    • On author's website or institutional repository
    • On funders designated website/repository after 12 months at the funders request or as a result of legal obligation
    • Published source must be acknowledged
    • Must link to publisher version
    • Set phrase to accompany link to published version (The original publication is available at www.springerlink.com)
    • Articles in some journals can be made Open Access on payment of additional charge
  • Classification
    ​ green

Publications in this journal

  • [Show abstract] [Hide abstract]
    ABSTRACT: Smart camera, i.e. cameras that are able to acquire and process images in real-time, is a typical example of the new embedded computer vision systems. A key example of application is automatic fall detection, which can be useful for helping elderly people in daily life. In this paper, we propose a methodology for development and fast-prototyping of a fall detection system based on such a smart camera, which allows to reduce the development time compared to standard approaches. Founded on a supervised classification approach, we propose a HW/SW implementation to detect falls in a home environment using a single camera and an optimized descriptor adapted to real-time tasks. This heterogeneous implementation is based on Xilinx’s system-on-chip named Zynq. The main contributions of this work are (i) the proposal of a co-design methodology. These methodologies enable the HW/SW partitioning to be delayed using high-level algorithmic description and high-level synthesis tools. Our approach enables fast prototyping which allows fast architecture exploration and optimisation to be performed, (ii) the design of a hardware accelerator dedicated to boosting-based classification, which is a very popular and efficient algorithm used in image analysis, (iii) the proposal of fall-detection embedded in a smart camera and enabling integration into the elderly people environment. Performances of our system are finally compared to the state-of-the-art.
    Journal of Real-Time Image Processing 10/2014;
  • [Show abstract] [Hide abstract]
    ABSTRACT: New applications of smart devices interacting with other computing devices are recently providing interesting and feasible solutions in ubiquitous computing environments. In this study, we propose an interactive virtual aquarium system that interacts with a smart device as a user interface. We developed a virtual aquarium graphic system and a remote interaction application of a smart device for building an interactive virtual aquarium system. We performed an experiment that demonstrates the feasibility and the effectiveness of the proposed system as an example of a new type of interactive application of a smart display, where a smart device serves as a remote user interface.
    Journal of Real-Time Image Processing 09/2014;
  • [Show abstract] [Hide abstract]
    ABSTRACT: We propose a real-time approach to automatically generate photomosaic videos from a set of optimized images by taking advantage of CUDA GPU acceleration. Our approach divides an input image into smaller cells—usually rectangular cells—and replaces each cell with a small image of an appropriate color pattern. Photomosaics require a large set of tile images with a variety of patterns to create high-quality digital mosaic images. Because a large database of images requires longer processing time and larger storage space for searching patterns from the database, this requirement causes problems in developing a real-time system or mobile applications that have limited resources. This paper deals with a real-time video photomosaics using genetic feature selection method for building an optimized image set and taking advantage of CUDA to accelerate pattern searching that minimizes computation cost.
    Journal of Real-Time Image Processing 09/2014; 9(3).
  • [Show abstract] [Hide abstract]
    ABSTRACT: Video-coding systems require a large external memory bandwidth to encode a single video frame. Many modules of the current video encoders must access the external memory to read and write data resulting in large power consumption, since memory-related power is dominant in current digital systems. Moreover, external memory access represents an important performance bottleneck in current multimedia systems. In this sense, this article presents the Reference Frame Context Adaptive Variable-Length Coder (RFCAVLC), which is a low-complexity lossless solution to compress the reference data before storing them in the external memory. The proposed approach is based on Huffman codes and employs eight static code tables to avoid the cost of the on-the-fly statistical analysis. The best table to encode each block is selected at run time using a context evaluation, resulting in a context-adaptive configuration. The proposed RFCAVLC reaches an average compression ratio superior to 32 % for the evaluated video sequences. The RFCAVLC architectures, encoder, and decoder were designed and synthesized targeting FPGA and 65 nm TSMC standard cell library. The RFCAVLC design is able to reach real-time encoding for WQSXGA (3,200 × 2,048 pixels) at 33 fps. The RFCAVLC also achieves power savings related to external memory communication that exceed 30 % when processing HD 1,080p videos at 30 fps.
    Journal of Real-Time Image Processing 08/2014;
  • [Show abstract] [Hide abstract]
    ABSTRACT: Connected-component labeling and Euler number computing are two essential processing tasks for extracting objects’ features in a binary image for the pattern recognition, image analysis, and computer (robot) vision. In general, the two processing tasks are usually executed independently by different algorithms in different scans. This paper proposes a combinational algorithm for labeling connected components in a binary image and computing the Euler number of the image simultaneously. In our algorithm, for the current pixel, the two processing tasks use the same information obtained from its neighbor pixels in the same scan. Moreover, the information obtained during processing the current pixel will be used for processing the next pixel. Our method is simple in principle and powerful in practice. Experimental results demonstrated that our method is much more efficient than conventional methods on various kinds of images, either in the case where the Euler number is calculated alone or in the case where both connected-component labeling and the Euler number computing are necessary.
    Journal of Real-Time Image Processing 06/2014;
  • [Show abstract] [Hide abstract]
    ABSTRACT: Effective compound image compression algorithms require compound images to be first segmented into regions such as text, pictures and background to minimize the loss of visual quality of text during compression. In this paper, a new compound image segmentation algorithm based on the Mixed Raster Content model (MRC) of multilayer approach is proposed (foreground/mask/background). This algorithm first segments a compound image into different classes. Then each class is transformed to the three-layer MRC model differently according to the property of that class. Finally, the foreground and the background layers are compressed using JPEG 2000. The mask layer is compressed using JBIG2. The proposed morphological-based segmentation algorithm design a binary segmentation mask which partitions a compound image into different layers, such as the background layer and the foreground layer accurately. Experimental results show that it is more robust with respect to the font size, style, colour, orientation, and alignment of text in an uneven background. At similar bit rates, our MRC compression with the morphology-based segmentation achieves a much higher subjective quality and coding efficiency than the state-of-the-art compression algorithms, such as JPEG, JPEG 2000 and H.264/AVC-I.
    Journal of Real-Time Image Processing 06/2014;
  • [Show abstract] [Hide abstract]
    ABSTRACT: Three dimensional range data provides useful information for various computer vision and computer graphics applications. For these, extracting the range data reliably is of utmost importance. Therefore, various range scanners based on different working principles are proposed in the literature. Among these, coded structured light-based range scanners are popular and used in most industrial applications. Unfortunately, these range scanners cannot scan shiny objects reliably. Either highlights on the shiny object surface or the ambient light in the environment disturb the code word. As the code is changed, the range data extracted from it will also be disturbed. In this study, we focus on developing a system that can scan shiny and matte objects under ambient light. Therefore, we propose color invariant-based binary, ternary, and quaternary coded structured light-based range scanners. We hypothesize that, by using color invariants, we can eliminate the effect of highlights and ambient light in the scanning process. Thus, we can extract the range data of shiny and matte objects in a robust manner. We implemented these scanners using a TI DM6437 EVM board with a flexible system setup such that the user can select the scanning type. Furthermore, we implemented a TI MSP430 microcontroller-based rotating table system that accompanies our scanner. With the help of this system, we can obtain the range data of the target object from different viewpoints. We also implemented a range image registration method to obtain the complete object model from the range data extracted. We tested our scanner system on various objects and provided their range and model data.
    Journal of Real-Time Image Processing 06/2014;
  • [Show abstract] [Hide abstract]
    ABSTRACT: The Hough transform is a well-known and popular algorithm for detecting lines in raster images. The standard Hough transform is rather slow to be usable in real time, so different accelerated and approximated algorithms exist. This study proposes a modified accumulation scheme for the Hough transform, using a new parameterization of lines “PClines”. This algorithm is suitable for computer systems with a small but fast read-write memory, such as today’s graphics processors. The algorithm requires no floating-point computations or goniometric functions. This makes it suitable for special and low-power processors and special-purpose chips. The proposed algorithm is evaluated both on synthetic binary images and on complex real-world photos of high resolutions. The results show that using today’s commodity graphics chips, the Hough transform can be computed at interactive frame rates, even with a high resolution of the Hough space and with the Hough transform fully computed.
    Journal of Real-Time Image Processing 03/2014;
  • [Show abstract] [Hide abstract]
    ABSTRACT: The stable Euler-number-based image binarization has been shown to give excellent visual results for images containing high amount of image noise. Being computationally expensive, its applications are limited mostly to general-purpose processors and in application specific integrated circuits. In this paper a modified stable Euler-number-based algorithm for image binarization is proposed and its real-time hardware implementation in a Field Programmable Gate Array with a pipelined architecture is presented. The proposed modifications to the algorithm facilitate hardware implementation. The end result is a design that out-performs known software implementations. The amount of noisy pixels introduced during the binarization process is also minimized. Despite the stable Euler-number-based image binarization being computationally expensive, our simulations show that the proposed architecture gives accurate results and this in real time and without consuming all chip resources.
    Journal of Real-Time Image Processing 03/2014;
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    ABSTRACT: State-of-the-art field-programmable gate array (FPGA) technologies have provided exciting opportunities to develop more flexible, less expensive, and better performance floating-point computing platforms for embedded systems. To better harness the full power of FPGAs and to bring FPGAs to more system designers, we investigate unique advantages and optimization opportunities in both software and hardware offered by multi-core processors on a programmable chip (MPoPCs). In this paper, we present our hardware customization and software dynamic scheduling solutions for LU factorization of large sparse matrices on in-house developed MPoPCs. Theoretical analysis is provided to guide the design. Implementation results on an Altera Stratix III FPGA for five benchmark matrices of size up to 7,917 × 7,917 are presented. Our hardware customization alone can reduce the execution time by up to 17.22 %. The integrated hardware–software optimization improves the speedup by an average of 60.30 %.
    Journal of Real-Time Image Processing 03/2014;
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    ABSTRACT: Dealing with visual data is the key for environmental monitoring tasks in Wireless Multimedia Sensor Networks (WMSNs). Tasks such as object detection, recognition, and/or tracking do require extracting and using the right information from the inherently large amount of visual data. The widely accepted solution of legacy WSNs, transmitting the acquired data to a central base station for further processing, would render a WMSN totally useless because of the unacceptable use of bandwidth and energy. Therefore, we consider the in situ processing as a viable solution for WMSNs. However, processing power and memory capacity restrictions of existing multimedia sensor nodes along with their power consumption are the limiting factors for wide-spread use of in situ processing. Nevertheless, recent technological improvements and introduction of the new ARM cores encourage us to evaluate the image processing capabilities of ARM7/ARM9/ARM11 based micro-controllers for in situ processing in WMSNs. In this work, we first discussed the architectural design differences among the various ARM cores. Then we classified image processing algorithms into three categories. Then, we evaluated the performance of each microcontroller by running a set of basic image processing algorithms necessary for object detection, recognition, and/or tracking. The test results show that ARM11 runs up to 6–30 times faster than ARM9 and ARM7, respectively. Besides, ARM11 consumes up to 5–7 times less energy than ARM9 and ARM7 for the same type of operations.
    Journal of Real-Time Image Processing 03/2014;
  • [Show abstract] [Hide abstract]
    ABSTRACT: The automatic detection of road signs is an application that alerts the vehicle’s driver of the presence of signals and invites him to react on time in the aim to avoid potential traffic accidents. This application can thus improve the road safety of persons and vehicles traveling in the road. Several techniques and algorithms allowing automatic detection of road signs are developed and implemented in software and do not allow embedded application. We propose in this work an efficient algorithm and its hardware implementation in an embedded system running in real time. In this paper we propose to implement the application of automatic recognition of road signs in real time by optimizing the techniques used in different phases of the recognition process. The system is implemented in a Virtex4 FPGA family which is connected to a camera mounted in the moving vehicle. The system can be integrated into the dashboard of the vehicle. The performance of the system shows a good compromise between speed and efficiency.
    Journal of Real-Time Image Processing 03/2014;
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    ABSTRACT: Nowadays, it is possible to build a multi-GPU supercomputer, well suited for implementation of digital signal processing algorithms, for a few thousand dollars. However, to achieve the highest performance with this kind of architecture, the programmer has to focus on inter-processor communications, tasks synchronization. In this paper, we propose a high level programming model based on a data flow graph (DFG) allowing an efficient implementation of digital signal processing applications on a multi-GPU computer cluster. This DFG-based design flow abstracts the underlying architecture. We focus particularly on the efficient implementation of communications by automating computation–communication overlap, which can lead to significant speedups as shown in the presented benchmark. The approach is validated on three experiments: a multi-host multi-gpu benchmark, a 3D granulometry application developed for research on materials and an application for computing visual saliency maps.
    Journal of Real-Time Image Processing 03/2014;
  • [Show abstract] [Hide abstract]
    ABSTRACT: The first step in any fingerprint recognition system is the fingerprint acquisition. A well-acquired fingerprint image results in high-resolution accuracy and low computational effort of processing. Hence, it is very useful for the recognition system to evaluate recognition confidence level to request new fingerprint samples if the confidence level is low, and to facilitate recognition process if the confidence level is high. This paper presents a hardware solution to ensure a successful and friendly acquisition of the fingerprint image, which can be incorporated at low cost into an embedded fingerprint recognition system due to its small size and high speed. The solution implements a novel technique based on directional image processing that allows not only the estimation of fingerprint image quality, but also the extraction of useful information (in particular, singular points). The digital architecture of the module is detailed and their features in terms of resource consumption and processing speed are illustrated with implementation results into FPGAs from Xilinx. Performance of the solution has been verified with fingerprints from several standard databases that have been acquired with sensors of different sizes and technologies (optical, capacitive, and thermal sweeping).
    Journal of Real-Time Image Processing 03/2014;
  • [Show abstract] [Hide abstract]
    ABSTRACT: Nowadays, hardware implementation of image and video processing algorithms on application specific integrated circuit (ASIC) has become a viable target in many applications. Star tracking algorithm is commonly used in space missions to recover the attitude of the satellite or spaceship. The algorithm matches stars of the satellite camera with the stars in a catalog to calculate the camera orientation (attitude). The number of stars in the catalog has the major impact on the accuracy of the star tracking algorithm. However, the higher number of stars in the catalog increases the computation burden and decreases the update rate of the algorithm. Hardware implementation of the star tracking algorithm using parallel and pipelined architecture is a proper solution to ensure higher accuracy as well as higher update rate. Noise filtering and also the detection of stars and their centroids in the camera image are the main stages in most of the star tracking algorithms. In this paper, we propose a new hardware architecture for star detection and centroid calculation in star tracking applications. The method contains several stages, including noise smoothing with fast Gaussian and median filters, connected component labeling, and centroid calculation. We introduce a new and fast algorithm for star labeling and centroid calculation that needs only one scan of the input image.
    Journal of Real-Time Image Processing 03/2014;
  • [Show abstract] [Hide abstract]
    ABSTRACT: The potential computational power of today multicore processors has drastically improved compared to the single processor architecture. Since the trend of increasing the processor frequency is almost over, the competition for increased performance has moved on the number of cores. Consequently, the fundamental feature of system designs and their associated design flows and tools need to change, so that, to support the scalable parallelism and the design portability. The same feature can be exploited to design reconfigurable hardware, such as FPGAs, which leads to rethink the mapping of sequential algorithms to HDL. The sequential programming paradigm, widely used for programming single processor systems, does not naturally provide explicit or implicit forms of scalable parallelism. Conversely, dataflow programming is an approach that naturally provides parallelism and the potential to unify SW and HDL designs on heterogeneous platforms. This study describes a dataflow-based design methodology aiming at a unified co-design and co-synthesis of heterogeneous systems. Experimental results on the implementation of a JPEG codec and a MPEG 4 SP decoder on heterogeneous platforms demonstrate the flexibility and capabilities of this design approach.
    Journal of Real-Time Image Processing 03/2014;